Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9484076 | Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features | LeeLean Shu, Yoshi Sato | 2016-11-01 |
| 9431079 | Systems and methods of memory and memory operation involving input latching, self-timing and/or other features | LeeLean Shu, Yoshi Sato | 2016-08-30 |
| 9159391 | Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features | LeeLean Shu, Yoshi Sato | 2015-10-13 |
| 9135986 | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features | Lee-Lean Shu, Chenming W. Tung | 2015-09-15 |
| 8693236 | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features | LeeLean Shu, Chenming W. Tung | 2014-04-08 |
| 8593860 | Systems and methods of sectioned bit line memory arrays | LeeLean Shu, Chenming W. Tung | 2013-11-26 |