Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8379466 | Integrated circuit having an embedded memory and method for testing the memory | Shayan Zhang, James D. Burnett, Kent P. Fancher, Michael D. Snyder | 2013-02-19 |
| 8315117 | Integrated circuit memory having assisted access and method therefor | Shayan Zhang, Troy L. Cooper, Jack M. Higman, Prashant U. Kenkare | 2012-11-20 |
| 8284593 | Multi-port memory having a variable number of used write ports | Shayan Zhang | 2012-10-09 |
| 8156357 | Voltage-based memory size scaling in a data processing system | Shayan Zhang, James D. Burnett, Prashant U. Kenkare, Hema Ramamurthy, Michael D. Snyder | 2012-04-10 |
| 8059482 | Memory using multiple supply voltages | Prashant U. Kenkare, Shayan Zhang | 2011-11-15 |
| 8009489 | Memory with read cycle write back | Shayan Zhang, Jack M. Higman, Prashant U. Kenkare, Pelley H. Perry | 2011-08-30 |
| 8004907 | SRAM with read and write assist | Troy L. Cooper, Prashant U. Kenkare, Shayan Zhang | 2011-08-23 |
| 7903483 | Integrated circuit having memory with configurable read/write operations and method therefor | Shayan Zhang | 2011-03-08 |
| 7863963 | Level shifter for change of both high and low voltage | Shayan Zhang, Hector Sanchez | 2011-01-04 |
| 7793172 | Controlled reliability in an integrated circuit | Klas Magnus Bruce, Shayan Zhang, Bradford Lawrence Hunter | 2010-09-07 |
| 7684264 | Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array | Bradford Lawrence Hunter, James D. Burnett, Shayan Zhang | 2010-03-23 |
| 7675806 | Low voltage memory device and method thereof | Bradford Hunter, David Burnett, Troy L. Cooper, Prashant U. Kenkare, Ravindraj Ramaraju +2 more | 2010-03-09 |
| 7542369 | Integrated circuit having a memory with low voltage read/write operation | Prashant U. Kenkare, David R. Bearden, James D. Burnett, Troy L. Cooper, Shayan Zhang | 2009-06-02 |
| 7525866 | Memory circuit | — | 2009-04-28 |
| 7523373 | Minimum memory operating voltage technique | David R. Bearden, Bradford Lawrence Hunter, Shayan Zhang | 2009-04-21 |
| 7499342 | Dynamic module output device and method thereof | Maciej Bajkowski, Ravindraraj Ramaraju | 2009-03-03 |
| 7492627 | Memory with increased write margin bitcells | Prashant U. Kenkare, Perry H. Pelley | 2009-02-17 |
| 7443745 | Byte writeable memory with bit-column voltage selection and column redundancy | — | 2008-10-28 |
| 7414449 | Dynamic scannable latch and method of operation | Jingfang Hao | 2008-08-19 |
| 7328731 | Vacuum release device and method | — | 2008-02-12 |
| 7292495 | Integrated circuit having a memory with low voltage read/write operation | Prashant U. Kenkare, David R. Bearden, James D. Burnett, Troy L. Cooper, Shayan Zhang | 2007-11-06 |
| 7140402 | Vacuum storage system and method | — | 2006-11-28 |