Issued Patents All Time
Showing 126–150 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5851881 | Method of making monos flash memory for multi-level logic | Ruei-Ling Lin, Mong-Song Liang | 1998-12-22 |
| 5851879 | Method for fabricating compact contactless trenched flash memory cell | Ruei-Ling Lin, Gary Hong | 1998-12-22 |
| 5834806 | Raised-bitline, contactless, trenched, flash memory cell | Ruei-Ling Lin, Mong-Song Liang | 1998-11-10 |
| 5818085 | Body contact for a MOSFET device fabricated in an SOI layer | Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung | 1998-10-06 |
| 5804858 | Body contacted SOI MOSFET | Mong-Song Liang | 1998-09-08 |
| 5796141 | Compact contactless trenched flash memory cell | Ruei-Ling Lin, Gary Hong | 1998-08-18 |
| 5796142 | SOI compact contactless flash memory cell | Ruei-Ling Lin, Gary Hong | 1998-08-18 |
| 5728613 | Method of using an insulator spacer to form a narrow base width lateral bipolar junction transistor | Steve S. Chung, Shyh-Chyi Wong, Mong-Song Liang | 1998-03-17 |
| 5726070 | Silicon-rich tunnel oxide formed by oxygen implantation for flash EEPROM | Gary Hong | 1998-03-10 |
| 5714412 | Multi-level, split-gate, flash memory cell and method of manufacture thereof | Mong-Song Liang, Di-Son Kuo, Ruei-Ling Lin | 1998-02-03 |
| 5705839 | Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology | Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung | 1998-01-06 |
| 5693974 | Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron MOSFETS | Mong-Song Liang | 1997-12-02 |
| 5679591 | Method of making raised-bitline contactless trenched flash memory cell | Ruei-Ling Lin, Mong-Song Liang | 1997-10-21 |
| 5646431 | Surface breakdown reduction by counter-doped island in power mosfet | Da-Chi Kuo | 1997-07-08 |
| 5610087 | Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer | Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung | 1997-03-11 |
| 5591650 | Method of making a body contacted SOI MOSFET | Mong-Song Liang | 1997-01-07 |
| 5573961 | Method of making a body contact for a MOSFET device fabricated in an SOI layer | Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung | 1996-11-12 |
| 5567631 | Method of forming gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology | Shyh-Chyi Wong, Mong-Song Liang, Steve S. Chung | 1996-10-22 |
| 5567635 | Method of making a three dimensional trench EEPROM cell structure | Alexandre Acovic, Being S. Wu | 1996-10-22 |
| 5521105 | Method of forming counter-doped island in power MOSFET | D. C. Kuo | 1996-05-28 |
| 5504031 | Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron mosfets | Mong-Song Liang | 1996-04-02 |
| 5482888 | Method of manufacturing a low resistance, high breakdown voltage, power MOSFET | Ta-Chi Kuo, Nai-Jen Yeh, Su-Yu Lu | 1996-01-09 |
| 5389567 | Method of forming a non-volatile DRAM cell | Alexandre Acovic, Matthew R. Wordeman, Being S. Wu | 1995-02-14 |
| 5331188 | Non-volatile DRAM cell | Alexandre Acovic, Matthew R. Wordeman, Being S. Wu | 1994-07-19 |
| 5315142 | High performance trench EEPROM cell | Alexandre Acovic, Being S. Wu | 1994-05-24 |