Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8643124 | Oxide-nitride-oxide stack having multiple oxynitride layers | Krishnaswamy Ramkumar, Fredrick B. Jenne, Sam Geha | 2014-02-04 |
| 8637921 | Nitridation oxidation of tunneling layer for improved SONOS speed and retention | Krishnaswamy Ramkumar, Fredrick B. Jenne | 2014-01-28 |
| 8633537 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Igor Polishchuk, Krishnaswamy Ramkumar | 2014-01-21 |
| 8614124 | SONOS ONO stack scaling | Fredrick B. Jenne | 2013-12-24 |
| 8592891 | Methods for fabricating semiconductor memory with process induced strain | Igor Polishchuk, Krishnaswamy Ramkumar, Jeong Soo Byun | 2013-11-26 |
| 8318608 | Method of fabricating a nonvolatile charge trap memory device | Krishnaswamy Ramkumar, Jeong Soo Byun | 2012-11-27 |
| 8163660 | SONOS type stacks for nonvolatile change trap memory devices and methods to form the same | Helmut Puchner, Igor Polishchuk | 2012-04-24 |
| 8093128 | Integration of non-volatile charge trap memory devices and logic CMOS devices | William Koutny, Sam Geha, Igor G. Kouznetsov, Krishnaswamy Ramkumar, Fredrick B. Jenne +2 more | 2012-01-10 |
| 8088683 | Sequential deposition and anneal of a dielectic layer in a charge trapping memory device | Krishnaswamy Ramkumar | 2012-01-03 |
| 8067284 | Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer | — | 2011-11-29 |
| 8063434 | Memory transistor with multiple charge storing layers and a high work function gate electrode | Igor Polishchuk, Krishnaswamy Ramkumar | 2011-11-22 |
| 7898852 | Trapped-charge non-volatile memory with uniform multilevel programming | Krishnaswamy Ramkumar, Peter Voss | 2011-03-01 |
| 7880219 | Nonvolatile charge trap memory device having <100> crystal plane channel orientation | Igor Polishchuk, Krishnaswamy Ramkumar | 2011-02-01 |
| 7799670 | Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices | Krishnaswamy Ramkumar, Jeong Soo Byun | 2010-09-21 |
| 7670963 | Single-wafer process for fabricating a nonvolatile charge trap memory device | Krishnaswamy Ramkumar | 2010-03-02 |
| 7446063 | Silicon nitride films | Mehran Sedigh | 2008-11-04 |
| 7384833 | Stress liner for integrated circuits | Igor Polishchuk, Krishnaswamy Ramkumar | 2008-06-10 |
| 6884719 | Method for depositing a coating having a relatively high dielectric constant onto a substrate | Jane Chang, You-Sheng Lin, Avishai Kepten, Michael Sendler, Robin Bloom | 2005-04-26 |
| 6638876 | Method of forming dielectric films | Robin Bloom, Avashai Kepten | 2003-10-28 |
| 6451713 | UV pretreatment process for ultra-thin oxynitride formation | Sing-Pin Tay, Yao Zhi Hu, Jeffrey C. Gelpey | 2002-09-17 |
| 6204120 | Semiconductor wafer pretreatment utilizing ultraviolet activated chlorine | Yitzhak Gilboa, Benjamin Brosilow, Hedvi Spielberg, Itai Bransky | 2001-03-20 |
| 6191011 | Selective hemispherical grain silicon deposition | Yitzhak Gilboa, Benjamin Brosilow, Hedvi Spielberg, Itai Bransky | 2001-02-20 |