Issued Patents All Time
Showing 26–50 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5822571 | Synchronizing data between devices | Alan L. Goodrum, Jens K. Ramsey, Joseph P. Miller | 1998-10-13 |
| 5819053 | Computer system bus performance monitoring | Alan L. Goodrum | 1998-10-06 |
| 5737604 | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | David A. Miller, Kenneth A. Jansen, Mark Taylor, Javier F. Izquierdo | 1998-04-07 |
| 5611078 | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | David A. Miller, Kenneth A. Jansen, Mark Taylor, Javier F. Izquierdo | 1997-03-11 |
| 5553310 | Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems | Mark Taylor, Maria L. Melo, Roger E. Tipley | 1996-09-03 |
| 5553248 | System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal | Maria L. Melo, Jeff W. Wolford, Michael Moriarty, Arnold Thomas Schnell | 1996-09-03 |
| 5519839 | Double buffering operations between the memory bus and the expansion bus of a computer system | Mark Taylor | 1996-05-21 |
| 5517624 | Multiplexed communication protocol between central and distributed peripherals in multiprocessor computer systems | John A. Landry, Dale J. Mayer | 1996-05-14 |
| 5465360 | Method and apparatus for independently resetting processors and cache controllers in multiple processor systems | David A. Miller, Kenneth A. Jansen, Mark Taylor, Javier F. Izquierdo | 1995-11-07 |
| 5463761 | Extended duration high resolution timer contained in two integrated circuits and having alternating data sequences provided from different integrated circuits | — | 1995-10-31 |
| 5442753 | Circuitry for providing replica data transfer signal during DMA verify operations | Timothy K. Waldrop | 1995-08-15 |
| 5437042 | Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system | John A. Landry, Dale J. Mayer, Christopher C. Wanner, Guy E. McSwain | 1995-07-25 |
| 5406590 | Method of and apparatus for correcting edge placement errors in multiplying phase locked loop circuits | Joseph P. Miller | 1995-04-11 |
| 5392436 | Two level system bus arbitration having lower priority multiprocessor arbitration and higher priority in a single processor and a plurality of bus masters arbitration | Kenneth A. Jansen, Montgomery C. McGraw, David A. Miller | 1995-02-21 |
| 5367689 | Apparatus for strictly ordered input/output operations for interrupt system integrity | Dale J. Mayer, John A. Landry | 1994-11-22 |
| 5341494 | Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals | John S. Thayer, Dale J. Mayer, Javier F. Izquierdo, John A. Landry | 1994-08-23 |
| 5307476 | Floppy disk controller with DMA verify operations | Timothy K. Waldrop | 1994-04-26 |
| 5303364 | Paged memory controller | Dale J. Mayer, Mark Taylor | 1994-04-12 |
| 5247685 | Interrupt handling in an asymmetric multiprocessor computer system | John A. Landry | 1993-09-21 |
| 5214767 | Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes | Christopher C. Wanner, Alan L. Goodrum | 1993-05-25 |
| 5210847 | Noncacheable address random access memory | Gary W. Thome, James H. Nuckols, Gary Brasher | 1993-05-11 |
| 5168568 | Delaying arbitration of bus access in digital computers | John S. Thayer, Montgomery C. McGraw | 1992-12-01 |
| 5165037 | System for controlling the transferring of different widths of data using two different sets of address control signals | — | 1992-11-17 |
| 5163143 | Enhanced locked bus cycle control in a cache memory computer system | Mark Taylor | 1992-11-10 |
| 5159679 | Computer system with high speed data transfer capabilities | — | 1992-10-27 |