Issued Patents All Time
Showing 76–98 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7297578 | Method for producing a field effect transistor | Thomas Skotnicki, Joel Hartmann | 2007-11-20 |
| 7214597 | Electronic components and method of fabricating the same | Francois Leverd, Thomas Skotnicki | 2007-05-08 |
| 7202153 | Method for forming, under a thin layer of a first material, portions of another material and/or empty areas | Yves Thomas Laplanche, Laurent Pain | 2007-04-10 |
| 7202518 | Integrated dynamic random access memory element, array and process for fabricating such elements | Francois Jacquet, Philippe Candellier, Robin Cerutti, Pascale Mazoyer | 2007-04-10 |
| 7188411 | Process for forming portions of a compound material inside a cavity | Christophe Regnier, François Wacquant, Thomas Skotnicki | 2007-03-13 |
| 7141837 | High-density MOS transistor | Yves Morand, Thomas Skotnicki, Robin Cerutti | 2006-11-28 |
| 7041585 | Process for producing an integrated electronic component | Jessy Bustos, Christophe Regnier, François Wacquant, Brice Tavel, Thomas Skotnicki | 2006-05-09 |
| 6969878 | Surround-gate semiconductor device encapsulated in an insulating medium | Stephane Monfray, Thomas Skotnicki | 2005-11-29 |
| 6911366 | Method for forming contact openings on a MOS integrated circuit | Paul Ferreira | 2005-06-28 |
| 6908811 | RAM | Marc Piazza | 2005-06-21 |
| 6846690 | Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding fabrication process | Alexis Farcy, Pascal Ancey, Joaquin Torres | 2005-01-25 |
| 6828646 | Isolating trench and manufacturing process | Michel Marty, Francois Leverd, Joaquin Torres | 2004-12-07 |
| 6759304 | DRAM memory integration method | Marc Piazza, Francois Leverd | 2004-07-06 |
| 6740919 | RAM | Marc Piazza | 2004-05-25 |
| 6689655 | Method for production process for the local interconnection level using a dielectric conducting pair on pair | Francois Leverd, Paul Ferreira | 2004-02-10 |
| 6417072 | Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step | Renzo Maccagnan, Philippe Lacombe | 2002-07-09 |
| 6363294 | Method and system for semiconductor wafer fabrication process real-time in-situ interactive supervision | Jean Canteloup, Renzo Maccagnan, Jean-Phillippe Vassilakis | 2002-03-26 |
| 6342452 | Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask | Pascal Costaganna, Lars Heineck | 2002-01-29 |
| 6297089 | Method of forming buried straps in DRAMs | Edith Lattard, Renzo Maccagnan | 2001-10-02 |
| 6281068 | Method for buried plate formation in deep trench capacitors | David Cruau, Francois Leverd, Renzo Maccagnan, Eric Mass | 2001-08-28 |
| 5874345 | Method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches | Frederic Lebrun, Renzo Maccagnan | 1999-02-23 |
| 5807761 | Method for real-time in-situ monitoring of a trench formation process | Jean Canteloup | 1998-09-15 |
| 5658418 | Apparatus for monitoring the dry etching of a dielectric film to a given thickness in an integrated circuit | Jean Canteloup | 1997-08-19 |