NK

Naresh Kumar

CS Cadence Design Systems: 21 patents #34 of 2,263Top 2%
TC Time Warner Cable: 6 patents #116 of 344Top 35%
Oracle: 3 patents #4,017 of 14,854Top 30%
TH Thoughtspot: 3 patents #33 of 99Top 35%
SN Snowflake: 2 patents #266 of 448Top 60%
Rolls-Royce Plc: 2 patents #806 of 2,886Top 30%
DL Dso National Laboratories: 1 patents #14 of 34Top 45%
EQ Equinix: 1 patents #97 of 162Top 60%
ZS Zscaler: 1 patents #152 of 274Top 60%
IN Infinera: 1 patents #238 of 407Top 60%
HE Hewlett Packard Enterprise: 1 patents #2,081 of 4,473Top 50%
TI The Travelers Indemnity: 1 patents #134 of 251Top 55%
📍 Atrauli, NC: #1 of 1 inventorsTop 100%
Overall (All Time): #66,412 of 4,157,543Top 2%
44
Patents All Time

Issued Patents All Time

Showing 26–44 of 44 patents

Patent #TitleCo-InventorsDate
9843645 System and method for pushing smart alerts 2017-12-12
9727676 Method and apparatus for efficient generation of compact waveform-based timing models Sneh Saurabh 2017-08-08
9667777 Automated bulk provisioning of primary rate interface and SIP trunk telephone numbers Prasanna Nagaraj, Srinivas Guduru 2017-05-30
9633159 Method and system for performing distributed timing signoff and optimization Vipul Parikh, Lalit Bharat, Shagufta Siddique, Prashant Sethia 2017-04-25
9589096 Method and apparatus for integrating spice-based timing using sign-off path-based analysis Umesh Gupta, Vishnu Kumar, Manish Bansal, Manuj Verma, Prashant Sethia 2017-03-07
9529962 System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design Amit Dhuria, Pradeep Yadav, Manuj Verma, Prashant Sethia 2016-12-27
9405882 High performance static timing analysis system and method for input/output interfaces Amit Dhuria, Prashant Sethia, Jeannette Sutherland, Shashank Tripathi 2016-08-02
8938703 Method and apparatus for comprehension of common path pessimism during timing model extraction Sneh Saurabh, Igor Keller 2015-01-20
8863052 System and method for generating and using a structurally aware timing model for representative operation of a circuit design Amit Dhuria, Umesh Gupta, Pradeep Yadav, Prashant Sethia 2014-10-14
8788995 System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design Prashant Sethia, Amit Dhuria, Krishna Belkhale 2014-07-22
8635660 Dynamic constraints for query operations Raymond Ng, Ganesh Kirti, Thomas Keefe 2014-01-21
8239798 Methods, systems, and apparatus for variation aware extracted timing models Ratnakar Goyal, Harindranath Parmeswaran 2012-08-07
8220033 Method and apparatus for managing bootstrap credentials for credentials-storage systems Raymond Ng, Ganesh Kirti, Thomas Keefe 2012-07-10
8126958 System and method for billing system interface failover resolution Robert Perry 2012-02-28
8010594 System and method for billing system interface failover resolution Robert Perry 2011-08-30
7945960 Dynamic conditional security policy extensions Raymond Ng, Ganesh Kirti, Thomas Keefe 2011-05-17
6932300 Device for closing parachute packs 2005-08-23
4995593 Crucible having a movable dross collector comprising an induction coil David A. Ford, Gordon J. S. Higginbotham, David R. Pugh 1991-02-26
4986517 Apparatus for pouring molten metals David A. Ford, Gordon J. S. Higginbotham, David R. Pugh 1991-01-22