Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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George K. Celler — 23 Patents

ATAT&T: 7 patents #2,622 of 18,772Top 15%
STS.O.I. Tec Silicon On Insulator Technologies: 5 patents #32 of 155Top 25%
BLBell Telephone Laboratories: 4 patents #115 of 1,445Top 8%
WCWestern Electric Company: 3 patents #40 of 531Top 8%
SOSoitec: 2 patents #91 of 259Top 40%
RJRutgers, The State University Of New Jersey: 1 patents #651 of 1,498Top 45%
AGAgere Systems Guardian: 1 patents #274 of 810Top 35%
Lawrenceville, NJ: #45 of 646 inventorsTop 7%
New Jersey: #3,347 of 69,400 inventorsTop 5%
Overall (All Time): #178,160 of 4,157,543Top 5%
23 Patents All Time
George K. Celler has been granted 23 US patents while listed as an inventor at AT&T. The first was granted in 1980 and the most recent in September 2017. George K. Celler ranks #178,160 of 4,157,543 US inventors in our database (top 4.3%). Patent records list George K. Celler in Lawrenceville, NJ, US.

Issued Patents All Time

Showing 1–23 of 23 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9761493 Thin epitaxial silicon carbide wafer fabrication 2017-09-12
8299485 Substrates for monolithic optical circuits and electronic circuits 2012-10-30
8148242 Oxidation after oxide dissolution Oleg Kononchuk 2012-04-03
7968911 Relaxation of a strained layer using a molten layer 2011-06-28
7956436 Method of forming a device wafer with recyclable support 2011-06-07
7605055 Wafer with diamond layer 2009-10-20
7605054 Method of forming a device wafer with recyclable support 2009-10-20
7585792 Relaxation of a strained layer using a molten layer 2009-09-08
6388290 Single crystal silicon on polycrystalline silicon integrated circuits Yves Chabal 2002-05-14 $3,798,000
5656399 Process for making an x-ray mask Joseph A. Abate, Jerry Vhi-Yi Guo 1997-08-12 $24,619,000
5482802 Material removal with focused particle beams Lloyd R. Harriott, Ratnaji R. Kola 1996-01-09
5051326 X-Ray lithography mask and devices made therewith Lee E. Trimble 1991-09-24
4835113 Fabrication of dielectrically isolated devices with buried conductive layers Lee E. Trimble 1989-05-30
4676841 Fabrication of dielectrically isolated devices utilizing buried oxygen implant and subsequent heat treatment at temperatures above 1300.degree. C . 1987-06-30
4581814 Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation Pradip K. Roy, Donald G. Schimmel, Lee E. Trimble 1986-04-15
4497683 Process for producing dielectrically isolated silicon devices McDonald Robinson 1985-02-05
4494303 Method of making dielectrically isolated silicon devices David Lischner, McDonald Robinson 1985-01-22
4461670 Process for producing silicon devices David Lischner, McDonald Robinson 1984-07-24
4406709 Method of increasing the grain size of polycrystalline materials by directed energy-beams Harry J. Leamy, Lee E. Trimble 1983-09-27 $62,320,000
4258078 Metallization for integrated circuits Thomas E. Seidel 1981-03-24 $18,808,000
4249962 Method of removing contaminating impurities from device areas in a semiconductor wafer 1981-02-10 $19,144,000
4240843 Forming self-guarded p-n junctions by epitaxial regrowth of amorphous regions using selective radiation annealing Gabriel L. Miller 1980-12-23 $10,153,000
4234358 Patterned epitaxial regrowth using overlapping pulsed irradiation Lionel C. Kimerling, Harry J. Leamy, John M. Poate, George Arthur Rozgonyi 1980-11-18 $20,937,000