Issued Patents All Time
Showing 76–88 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7737036 | Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation | Yi Ma, Philip Allan Kraus, Khaled Ahmed, Abhilash J. Mayur | 2010-06-15 |
| 7727828 | Method for fabricating a gate dielectric of a field effect transistor | Thai Cheng Chua, Cory Czarnik, Andreas Hegedus, Khaled Ahmed, Philip Allan Kraus | 2010-06-01 |
| 7645710 | Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system | Thai Cheng Chua, Steven C. H. Hung, Patricia M. Liu, Tatsuya Sato, Alex Paterson +2 more | 2010-01-12 |
| 7611976 | Gate electrode dopant activation method for semiconductor manufacturing | Yi Ma, Khaled Ahmed, Kevin Cunningham, Robert C. McIntosh, Abhilash J. Mayur +6 more | 2009-11-03 |
| 7575986 | Gate interface relaxation anneal method for wafer processing with post-implant dynamic surface annealing | Sunderraj Thirupapuliyur | 2009-08-18 |
| 7569502 | Method of forming a silicon oxynitride layer | Faran Nouri, Thai Cheng Chua | 2009-08-04 |
| 7429538 | Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric | — | 2008-09-30 |
| 7429540 | Silicon oxynitride gate dielectric formation using multiple annealing steps | — | 2008-09-30 |
| 7122454 | Method for improving nitrogen profile in plasma nitrided gate dielectric layers | — | 2006-10-17 |
| 7078302 | Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal | Yi Ma, Khaled Ahmed, Kevin Cunningham, Robert C. McIntosh, Abhilash J. Mayur +6 more | 2006-07-18 |
| 6653200 | Trench fill process for reducing stress in shallow trench isolation | — | 2003-11-25 |
| 6313466 | Method for determining nitrogen concentration in a film of nitrided oxide material | Subhas Bothra | 2001-11-06 |
| 6150234 | Trench-diffusion corner rounding in a shallow-trench (STI) process | — | 2000-11-21 |