Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369299 | Devices and methods for DRAM leakage reduction | John Hautala, Yan Zhang, Johannes M. van Meer | 2025-07-22 |
| 12279410 | Epitaxial single crystalline silicon growth for a horizontal access device | Gurtej S. Sandhu, Scott E. Sills, Si-Woo Lee, John Smythe | 2025-04-15 |
| 12096622 | Directional etch for improved dual deck three-dimensional NAND architecture margin | John Hautala, Johannes M. van Meer | 2024-09-17 |
| 11987879 | High aspect ratio taper improvement using directional deposition | Yan Zhang, John Hautala | 2024-05-21 |
| 11942361 | Semiconductor device cavity formation using directional deposition | Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam | 2024-03-26 |
| 11778832 | Wordline contact formation in NAND devices | Tristan Y. Ma, Johannes M. van Meer, John Hautala, Naushad K. Variam | 2023-10-03 |
| 11476251 | Channel integration in a three-node access device for vertical three dimensional (3D) memory | Scott E. Sills, John Smythe, Si-Woo Lee, Gurtej S. Sandhu | 2022-10-18 |
| 11329051 | Gate dielectric repair on three-node access device formation for vertical three-dimensional (3D) memory | John Smythe, Gurtej S. Sandhu, Si-Woo Lee, Scott E. Sills | 2022-05-10 |
| 11289491 | Epitaxtal single crystalline silicon growth for a horizontal access device | Gurtej S. Sandhu, Scott E. Sills, Si-Woo Lee, John Smythe | 2022-03-29 |
| 11239117 | Replacement gate dielectric in three-node access device formation for vertical three dimensional (3D) memory | John Smythe, Si-Woo Lee, Gurtej S. Sandhu, Scott E. Sills | 2022-02-01 |
| 11227864 | Storage node after three-node access device formation for vertical three dimensional (3D) memory | John Smythe, Si-Woo Lee, Gurtej S. Sandhu, Scott E. Sills | 2022-01-18 |
| 11127588 | Semiconductor processing applying supercritical drying | Sevim Korkmaz, Sanjeev Sapra, Jerome A. Imonigie | 2021-09-21 |