Issued Patents All Time
Showing 26–50 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9727505 | Clock control for DMA busses | David G. Conroy, Joseph P. Bratt | 2017-08-08 |
| 9699481 | System and method for masking visual compression artifacts in decoded video streams | Haitao Guo, Sally Fung | 2017-07-04 |
| 9653079 | Clock switching in always-on component | Manu Gulati, Gilbert H. Herbeck, Alexei E. Kosut, Girault W. Jones | 2017-05-16 |
| 9619377 | System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode | Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki +3 more | 2017-04-11 |
| 9595514 | Package with SoC and integrated memory | John Bruno, Jun Zhai | 2017-03-14 |
| 9591219 | Modeless video and still frame capture | D. Amnon Silverstein, Shun Wai Go, Suk Hwan Lim, Ting Chen, Bin Ni | 2017-03-07 |
| 9571846 | Data storage and access in block processing pipelines | Mark P. Rygh, Craig M. Okruhlica, Jim C. Chou, Guy Cote, Gaurav S. Gulati +2 more | 2017-02-14 |
| 9529544 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, James B. Keller | 2016-12-27 |
| 9344626 | Modeless video and still frame capture using interleaved frames of video and still resolutions | D. Amnon Silverstein, Shun Wai Go, Suk Hwan Lim, Ting Chen, Bin Ni | 2016-05-17 |
| 9336558 | Wavefront encoding with parallel bit stream encoding | Guy Cote, Joseph Cheng, Mark P. Rygh, Jim C. Chou | 2016-05-10 |
| 9336563 | Buffer underrun handling | Joseph P. Bratt, Peter F. Holland, Shing Horng Choo, Brijesh Tripathi | 2016-05-10 |
| 9331058 | Package with SoC and integrated memory | John Bruno, Jun Zhai | 2016-05-03 |
| 9274953 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, James B. Keller | 2016-03-01 |
| 9262798 | Parameter FIFO | Joseph P. Bratt, Peter F. Holland, Shing Horng Choo | 2016-02-16 |
| 9224187 | Wavefront order to scan order synchronization | Guy Cote, Jim C. Chou, Manching Ko, Weichun Ku | 2015-12-29 |
| 9224186 | Memory latency tolerance in block processing pipelines | Mark P. Rygh, Guy Cote, Joseph Cheng | 2015-12-29 |
| 9218639 | Processing order in block processing pipelines | Guy Cote, Mark P. Rygh, Jim C. Chou, Joseph Cheng | 2015-12-22 |
| 9215472 | Parallel hardware and software block processing pipelines | James E. Orr, Joseph Cheng, Nitin Bhargava, Guy Cote | 2015-12-15 |
| 9176913 | Coherence switch for I/O traffic | Muditha Kanchana, Shailendra Desai | 2015-11-03 |
| 9087393 | Network display support in an integrated circuit | Brijesh Tripathi, Peter F. Holland | 2015-07-21 |
| 9081517 | Hardware-based automatic clock gating | Kleanthes G. Koniaris, Josh P. de Cesare, Jung Wook Cho, Erik P. Machnicki | 2015-07-14 |
| 9032113 | Clock control for DMA busses | David G. Conroy, Joseph P. Bratt | 2015-05-12 |
| 8977818 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, James B. Keller | 2015-03-10 |
| 8963587 | Clock generation using fixed dividers and multiplex circuits | Erik P. Machnicki, Raman S. Thiara, Shane J. Keil | 2015-02-24 |
| 8959369 | Hardware automatic performance state transitions in system on processor sleep and wake events | Josh P. de Cesare, Jung Wook Cho, Toshinari Takayanagi | 2015-02-17 |