Issued Patents All Time
Showing 76–91 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8244981 | Combined transparent/non-transparent cache | James Wang, Zongjian Chen, James B. Keller | 2012-08-14 |
| 8219758 | Block-based non-transparent cache | James Wang, Zongjian Chen, James B. Keller | 2012-07-10 |
| 8181059 | Inter-processor communication channel including power-down functionality | Binu K. Mathew, Stephan V. Schell | 2012-05-15 |
| 8099528 | Data filtering using central DMA mechanism | David G. Conroy, Michael Culbert | 2012-01-17 |
| 7984317 | Hardware-based power management of functional blocks | David G. Conroy, Joseph P. Bratt | 2011-07-19 |
| 7593336 | Logical ports in trunking | Surya P. Varanasi | 2009-09-22 |
| 7460537 | Supplementary header for multifabric and high port count switch support in a fibre channel network | Surya P. Varanasi, Zahid Hussain, Kung-Ling Ko | 2008-12-02 |
| 7443799 | Load balancing in core-edge configurations | Surya P. Varanasi, Kung-Ling Ko | 2008-10-28 |
| 7430203 | Fibre channel zoning hardware for directing a data packet to an external processing device | Surya P. Varanasi, Indraneel Ghosh, Zahid Hussain | 2008-09-30 |
| 7042460 | Method and apparatus for rasterizing in a hierarchical tile order | Zahid Hussain | 2006-05-09 |
| 6972768 | Method and apparatus for rasterizing in a hierarchical tile order | Zahid Hussain | 2005-12-06 |
| 6791569 | Antialiasing method using barycentric coordinates applied to lines | Zahid Hussain | 2004-09-14 |
| 6611272 | Method and apparatus for rasterizing in a hierarchical tile order | Zahid Hussain | 2003-08-26 |
| 6380942 | Packetized command interface to a graphics processor | Zahid Hussain | 2002-04-30 |
| 6331857 | Packetized command interface to a graphics processor | Zahid Hussain | 2001-12-18 |
| 6075546 | Packetized command interface to graphics processor | Zahid Hussain | 2000-06-13 |