Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11392508 | Lightweight address translation for page migration and duplication | Nuwan Jayasena | 2022-07-19 |
| 11360891 | Adaptive cache reconfiguration via clustering | Mohamed Assem Abd ElMohsen Ibrahim, Onur Kayiran, Gabriel H. Loh | 2022-06-14 |
| 11226900 | Using a bloom filter to reduce the number of memory addressees tracked by a coherence directory | Weon Taek Na, Mark H. Oskin, Gabriel H. Loh, William L. Walker, Michael W. Boyer | 2022-01-18 |
| 11068458 | Mechanism for distributed-system-aware difference encoding/decoding in graph analytics | Mohamed Assem Abd ElMohsen Ibrahim, Onur Kayiran | 2021-07-20 |
| 10984838 | Interconnect architecture for three-dimensional processing systems | Nuwan Jayasena | 2021-04-20 |
| 10970120 | Method and system for opportunistic load balancing in neural networks using metadata | Nicholas Malaya | 2021-04-06 |
| 10938709 | Mechanism for dynamic latency-bandwidth trade-off for efficient broadcasts/multicasts | Mohamed Assem Abd ElMohsen Ibrahim, Onur Kayiran, Jieming Yin | 2021-03-02 |
| 10853904 | Hierarchical register file at a graphics processing unit | Nuwan Jayasena | 2020-12-01 |
| 10838864 | Prioritizing local and remote memory access in a non-uniform memory access architecture | Michael W. Boyer, Onur Kayiran, Steven Raasch, Muhammad Shoaib Bin Altaf | 2020-11-17 |
| 10719441 | Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory access requests | Jieming Yin, Matthew R. Poremba, Steven Raasch, Doug Hunt | 2020-07-21 |
| 10705958 | Coherency directory entry allocation based on eviction costs | Michael W. Boyer, Gabriel H. Loh, William L. Walker | 2020-07-07 |
| 10635588 | Distributed coherence directory subsystem with exclusive data regions | Maurice B. Steinman, Steven Raasch | 2020-04-28 |
| 10503640 | Selective data retrieval based on access latency | — | 2019-12-10 |
| 10452437 | Temperature-aware task scheduling and proactive power management | Abhinandan Majumdar, Brian J. Kocoloski, Leonardo Piga, Wei Huang | 2019-10-22 |
| 10389251 | Setting operating points for circuits in an integrated circuit chip | Wei-Ming Huang, Xudong An, Muhammad Shoaib Bin Altaf, Jieming Yin | 2019-08-20 |
| 10339067 | Mechanism for reducing page migration overhead in memory systems | Thiruvengadam Vijayaraghavan, Gabriel H. Loh | 2019-07-02 |
| 10310981 | Method and apparatus for performing memory prefetching | Nuwan Jayasena, Reena Panda, Onur Kayiran, Michael W. Boyer | 2019-06-04 |
| 10303602 | Preemptive cache management policies for processing units | Onur Kayiran, Gabriel H. Loh | 2019-05-28 |
| 10282295 | Reducing cache footprint in cache coherence directory | William L. Walker, Michael W. Boyer, Gabriel H. Loh | 2019-05-07 |
| 10198369 | Dynamic memory remapping to reduce row-buffer conflicts | Reena Panda, Nuwan Jayasena | 2019-02-05 |
| 10162757 | Proactive cache coherence | Nuwan Jayasena | 2018-12-25 |
| 10133678 | Method and apparatus for memory management | Syed Ali Jafri, Srilatha Manne, Gabriel H. Loh | 2018-11-20 |
| 10097091 | Setting operating points for circuits in an integrated circuit chip | Wei-Ming Huang, Xudong An, Muhammad Shoaib Bin Altaf, Jieming Yin | 2018-10-09 |
| 9947386 | Thermal aware data placement and compute dispatch in a memory system | Manish Arora, Indrani Paul, Nuwan Jayasena, Dong Zhang | 2018-04-17 |
| 9921635 | Dynamic and adaptive sleep state management | Manish Arora | 2018-03-20 |