Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9916265 | Traffic rate control for inter-class data migration in a multiclass memory system | Sergey Blagodurov, Gabriel H. Loh | 2018-03-13 |
| 9851777 | Power gating based on cache dirtiness | Manish Arora, Indrani Paul, Nuwan Jayasena, Srilatha Manne, Madhu Saravana Sibi Govindan +1 more | 2017-12-26 |
| 9818455 | Query operations for stacked-die memory device | Gabriel H. Loh, Nuwan Jayasena, James M. O'Connor | 2017-11-14 |
| 9766936 | Selecting a resource from a set of resources for performing an operation | Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu +1 more | 2017-09-19 |
| 9746908 | Pruning of low power state information for a processor | Derek Robert Hower, Marc S. Orr | 2017-08-29 |
| 9734059 | Methods and apparatus for data cache way prediction based on classification as stack data | Lena E. Olson, Vilas Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne | 2017-08-15 |
| 9710392 | Virtual memory mapping for improved DRAM page locality | Syed Ali Jafri, Srilatha Manne, Mithuna S. Thottethodi | 2017-07-18 |
| 9672161 | Configuring a cache management mechanism based on future accesses in a cache | Gabriel H. Loh | 2017-06-06 |
| 9658663 | Thermally-aware throttling in a three-dimensional processor stack | Wei Huang, Manish Arora, Indrani Paul | 2017-05-23 |
| 9529718 | Batching modified blocks to the same dram page | Syed Ali Jafri, Srilatha Manne, Mithuna S. Thottethodi, Gabriel H. Loh | 2016-12-27 |
| 9524164 | Specialized memory disambiguation mechanisms for different memory read access types | Lena E. Olson, Srilatha Manne | 2016-12-20 |
| 9507410 | Decoupled selective implementation of entry and exit prediction for power gating processor components | Manish Arora, Indrani Paul | 2016-11-29 |
| 9443561 | Ring networks for intra- and inter-memory I/O including 3D-stacked memories | David A. Roberts, Mitesh R. Meswani, Indrani Paul | 2016-09-13 |
| 9442557 | Using a linear prediction to configure an idle state of an entity in a computing device | Manish Arora, Nuwan Jayasena, Madhu Saravana Sibi Govindan, William L. Bircher, Michael Schulte +1 more | 2016-09-13 |
| 9378153 | Early write-back of modified data in a cache memory | Syed Ali Jafri, Srilatha Manne | 2016-06-28 |
| 9372803 | Method and system for shutting down active core based caches | Srilatha Manne, Michael Schulte, Lloyd Bircher, Madhu Saravana Sibi Govindan | 2016-06-21 |
| 9367455 | Using predictions for store-to-load forwarding | Lena E. Olson, Srilatha Manne, James M. O'Connor | 2016-06-14 |
| 9298615 | Methods and apparatus for soft-partitioning of a data cache for stack data | Lena E. Olson, Vilas Sridharan, James M. O'Connor, Mark D. Hill, Srilatha Manne | 2016-03-29 |
| 9286948 | Query operations for stacked-die memory device | Gabriel H. Loh, Nuwan Jayasena, James M. O'Connor | 2016-03-15 |
| 9251069 | Mechanisms to bound the presence of cache blocks with specific properties in caches | Gabriel H. Loh, Mauricio Breternitz, James M. O'Connor, Srilatha Manne, Nuwan Jayasena +1 more | 2016-02-02 |
| 9251081 | Management of caches | Kai K. Chang, Gabriel H. Loh, Lisa R. Hsu | 2016-02-02 |
| 9189399 | Stack cache management and coherence techniques | Lena E. Olson, Bradford M. Beckmann | 2015-11-17 |
| 9183055 | Selecting a resource from a set of resources for performing an operation | Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu +1 more | 2015-11-10 |
| 9128856 | Selective cache fills in response to write misses | Mithuna S. Thottethodi, Srilatha Manne | 2015-09-08 |
| 9110671 | Idle phase exit prediction | Srilatha Manne, William L. Bircher, Mahdu S. S. Govindan, Michael Schulte, Manish Arora | 2015-08-18 |