Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11398831 | Temporal link encoding | Onur Kayiran, Steven Raasch, Jagadish B. Kotra | 2022-07-26 |
| 11385983 | Hardware assisted memory profiling aggregator | Jinyoung Choi | 2022-07-12 |
| 11341059 | Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations | Andrew G. Kegel | 2022-05-24 |
| 11237928 | Method for a reliability, availability, and serviceability-conscious huge page support | Michael Ignatowski, Vilas Sridharan | 2022-02-01 |
| 11150899 | Selecting a precision level for executing a workload in an electronic device | Anthony Gutierrez, Scott A. Moe, Xianwei Zhang, Jieming Yin, Matthew D. Sinclair | 2021-10-19 |
| 11064019 | Dynamic configuration of inter-chip and on-chip networks in cloud computing system | — | 2021-07-13 |
| 10761986 | Redirecting data to improve page locality in a scalable data fabric | Timothy E. Landreth, Stanley A. Lackey, Jr., Patrick Conway | 2020-09-01 |
| 10678702 | Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations | Andrew G. Kegel | 2020-06-09 |
| 10592279 | Multi-processor apparatus and method of detection and acceleration of lagging tasks | Arkaprava Basu, Dmitri Yudanov, David A. Roberts, Mitesh R. Meswani | 2020-03-17 |
| 10318153 | Techniques for changing management modes of multilevel memory hierarchy | Mitesh R. Meswani, Gabriel H. Loh, Mauricio Breternitz, Mark Richard Nutter, John R. Slice +3 more | 2019-06-11 |
| 10318340 | NVRAM-aware data processing system | Gabriel H. Loh, Mauricio Breternitz | 2019-06-11 |
| 10261916 | Adaptive extension of leases for entries in a translation lookaside buffer | Amro Awad, Arkaprava Basu, Mark H. Oskin, Gabriel H. Loh, Andrew G. Kegel +2 more | 2019-04-16 |
| 10235290 | Hot page selection in multi-level memory hierarchies | Gabriel H. Loh, Mitesh R. Meswani | 2019-03-19 |
| 10171382 | Mechanism of identifying available memory resources in a network of multi-level memory modules | — | 2019-01-01 |
| 10121555 | Wear-limiting non-volatile memory | Amro Awad | 2018-11-06 |
| 10073746 | Method and apparatus for providing distributed checkpointing | Taniya Siddiqua, Vilas Sridharan | 2018-09-11 |
| 10055359 | Pinning objects in multi-level memory hierarchies | Gabriel H. Loh, John R. Slice | 2018-08-21 |
| 10019283 | Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread | Dmitri Yudanov, Arkaprava Basu, Sooraj Puthoor, Joseph L. Greathouse | 2018-07-10 |
| 9983655 | Method and apparatus for performing inter-lane power management | Mitesh R. Meswani, David A. Roberts, Dmitri Yudanov, Arkaprava Basu | 2018-05-29 |
| 9965329 | Method and apparatus for workload placement on heterogeneous systems | — | 2018-05-08 |
| 9934148 | Memory module with embedded access metadata | David A. Roberts | 2018-04-03 |
| 9916265 | Traffic rate control for inter-class data migration in a multiclass memory system | Gabriel H. Loh, Yasuko Eckert | 2018-03-13 |
| 9594521 | Scheduling of data migration | Andrew G. Kegel | 2017-03-14 |
| 9178763 | Weight-based collocation management | Daniel Juergen Gmach, Martin Arlitt, Yuan Chen, Chris D. Hyser | 2015-11-03 |
| 9104498 | Maximizing server utilization within a datacenter | Martin Arlitt, Daniel Juergen Gmach, Yuan Chen, Chris D. Hyser, Cullen E. Bash | 2015-08-11 |