Issued Patents All Time
Showing 101–125 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6643828 | Method for controlling critical circuits in the design of integrated circuits | Wayne Kever | 2003-11-04 |
| 6640283 | Apparatus for cache compression engine for data compression of on-chip caches to increase effective cache size | Wayne Kever | 2003-10-28 |
| 6631506 | Method and apparatus for identifying switching race conditions in a circuit design | Charles Pie, Timothy C. Fischer | 2003-10-07 |
| 6621310 | Reducing power consumption variability of precharge-pulldown busses | — | 2003-09-16 |
| 6622284 | Method and apparatus for detection of errors in one-hot words | Kevin Jones | 2003-09-16 |
| 6606720 | Scan structure for CMOS storage elements | — | 2003-08-12 |
| 6586971 | Adapting VLSI clocking to short term voltage transients | Eric Fetzer | 2003-07-01 |
| 6583650 | Latching annihilation based logic gate | Jayen Desai, Reid James Riedlinger | 2003-06-24 |
| 6560737 | Method for adding scan controllability and observability to domino CMOS with low area and delay overhead | Glenn T. Colon-Bonet, Barry J. Arnold, Thomas J. Sullivan | 2003-05-06 |
| 6556501 | Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations | — | 2003-04-29 |
| 6549605 | Limiting loss in a circuit | Don Douglas Josephson | 2003-04-15 |
| 6539527 | System and method of determining the noise sensitivity of an integrated circuit | John D Wanek | 2003-03-25 |
| 6509788 | System and method utilizing on-chip voltage controlled frequency modulation to manage power consumption | Don Douglas Josephson | 2003-01-21 |
| 6493855 | Flexible cache architecture using modular arrays | Donald R. Weiss | 2002-12-10 |
| 6489834 | System and method utilizing on-chip voltage monitoring to manage power consumption | Don Douglas Josephson | 2002-12-03 |
| 6483348 | Reducing power consumption variability of static busses | — | 2002-11-19 |
| 6466057 | Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method | — | 2002-10-15 |
| 6459304 | Latching annihilation based logic gate | Jayen Desai, Reid James Riedlinger | 2002-10-01 |
| 6448837 | Reduced current variability I/O bus termination | — | 2002-09-10 |
| 6446187 | Virtual address bypassing using local page mask | Reid James Riedlinger, Douglas J. Cutter, Christopher Seib | 2002-09-03 |
| 6377096 | Static to dynamic logic interface circuit | — | 2002-04-23 |
| 6366526 | Static random access memory (SRAM) array central global decoder system and method | Donald R. Weiss, John Wuu | 2002-04-02 |
| 6363006 | Asymmetric RAM cell | Donald R. Weiss | 2002-03-26 |
| 6359830 | Storage cell on integrated circuit responsive to plural frequency clocks | Eric Fetzer, Preston J Renstrom | 2002-03-19 |
| 6326829 | Pulse latch with explicit, logic-enabled one-shot | — | 2001-12-04 |