Issued Patents All Time
Showing 126–150 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6323714 | System and method for deskewing synchronous clocks in a very large scale integrated circuit | Eugene Berta, Gerard M. Blair, James S. Wells | 2001-11-27 |
| 6313675 | Delay locked loop driver | — | 2001-11-06 |
| 6301186 | RAM cell with column clear | — | 2001-10-09 |
| 6292041 | Circuit and method for limiting subthreshold leakage | — | 2001-09-18 |
| 6281710 | Selective latch for a domino logic gate | Christopher Allan Poirier | 2001-08-28 |
| 6265897 | Contention based logic gate driving a latch and driven by pulsed clock | Christopher Allan Poirier, Wayne Kever | 2001-07-24 |
| 6243287 | Distributed decode system and method for improving static random access memory (SRAM) density | Donald R. Weiss, John Wuu | 2001-06-05 |
| 6240009 | Asymmetric ram cell | Donald R. Weiss | 2001-05-29 |
| 6240038 | Low area impact technique for doubling the write data bandwidth of a memory array | Mike Barry | 2001-05-29 |
| 6188633 | Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations | — | 2001-02-13 |
| 6166946 | System and method for writing to and reading from a memory cell | — | 2000-12-26 |
| 6075386 | Dynamic logic gate with relaxed timing requirements and output state holding | — | 2000-06-13 |
| 6014732 | Cache memory with reduced access time | — | 2000-01-11 |
| 5949825 | Regenerative clamp for multi-drop busses | — | 1999-09-07 |
| 5900766 | Coupling charge compensation device for VLSI circuits | Jeffry D. Yetter | 1999-05-04 |
| 5901061 | Method of checking for races in a digital design | Neela B. Gaddis, Jonathan Lotz | 1999-05-04 |
| 5892698 | 2's complement floating-point multiply accumulate unit | — | 1999-04-06 |
| 5889979 | Transparent data-triggered pipeline latch | Robert H. Miller | 1999-03-30 |
| 5838944 | System for storing processor register data after a mispredicted branch | Donald Kipp, Gregg B. Lesartre, Jonathan Lotz | 1998-11-17 |
| 5815432 | Single-ended read, dual-ended write SCRAM cell | Kevin X. Zhang | 1998-09-29 |
| 5760608 | High speed, low clock load register dump circuit | Ricky L. Pettit | 1998-06-02 |
| 5760610 | Qualified universal clock buffer circuit for generating high gain, low skew local clock signals | — | 1998-06-02 |
| 5757686 | Method of decoupling the high order portion of the addend from the multiply result in an FMAC | David Richard Smentek | 1998-05-26 |
| 5757687 | Method and apparatus for bounding alignment shifts to enable at-speed denormalized result generation in an FMAC | Rodolfo G. Beraha | 1998-05-26 |
| 5719803 | High speed addition using Ling's equations and dynamic CMOS logic | — | 1998-02-17 |