Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8461893 | Uniform-footprint programmable multi-stage delay cell | Martin J. Gasper, Bruce E. Zahn | 2013-06-11 |
| 8271922 | System and method for clock optimization to achieve timing signoff in an electronic circuit and electronic design automation tool incorporating the same | Bruce E. Zahn | 2012-09-18 |
| 7944284 | System and circuit for a virtual power grid | — | 2011-05-17 |
| 6654712 | Method to reduce skew in clock signal distribution using balanced wire widths | — | 2003-11-25 |
| 6617900 | Arbitrator with no metastable voltage levels on output | — | 2003-09-09 |
| 6591371 | System for counting a number of clock cycles such that a count signal is diverted from a cascaded series of write latches to a cascaded series of erase latches | — | 2003-07-08 |
| 6323714 | System and method for deskewing synchronous clocks in a very large scale integrated circuit | Samuel D. Naffziger, Eugene Berta, James S. Wells | 2001-11-27 |