Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6067616 | Branch prediction device with two levels of branch prediction cache | David R. Stiles, John G. Favor | 2000-05-23 |
| 5881265 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1999-03-09 |
| 5815699 | Configurable branch prediction for a processor performing speculative execution | David L. Puziol, Larry Widigen, Len Shar, Walstein Bennett Smith, III | 1998-09-29 |
| 5802339 | Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit | Elliot A. Sowadsky, Larry Widigen, David L. Puziol | 1998-09-01 |
| 5781753 | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1998-07-14 |
| 5768575 | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1998-06-16 |
| 5748932 | Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence | David R. Stiles, John G. Favor | 1998-05-05 |
| 5682492 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1997-10-28 |
| 5675758 | Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations | Elliot A. Sowadsky, Larry Widigen, David L. Puziol | 1997-10-07 |
| 5649137 | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | John G. Favor, David R. Stiles | 1997-07-15 |
| 5623614 | Branch prediction cache with multiple entries for returns having multiple callers | Larry Widigen, David L. Puziol | 1997-04-22 |
| 5590351 | Superscalar execution unit for sequential instruction pointer updates and segment limit checks | Elliot A. Sowadsky, Larry Widigen, David L. Puziol | 1996-12-31 |
| 5515518 | Two-level branch prediction cache | David R. Stiles, John G. Favor | 1996-05-07 |
| 5511175 | Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | John G. Favor, David R. Stiles | 1996-04-23 |
| 5454117 | Configurable branch prediction for a processor performing speculative execution | David L. Puziol, Larry Widigen, Len Shar, Walstein Bennett Smith, III | 1995-09-26 |
| 5442757 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1995-08-15 |
| 5327547 | Two-level branch prediction cache | David R. Stiles, John G. Favor | 1994-07-05 |
| 5230068 | Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence | David R. Stiles, John G. Favor | 1993-07-20 |
| 5226126 | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags | Harold L. McFarland, David R. Stiles, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1993-07-06 |
| 5226130 | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | John G. Favor, David R. Stiles | 1993-07-06 |
| 5163140 | Two-level branch prediction cache | David R. Stiles, John G. Favor | 1992-11-10 |
| 5109524 | Digital processor with a four part data register for storing data before and after data conversion and data calculations | Lawrence F. Wagner, Jr., Wayne Burleson, Robert D. Hemming, John P. Guadagna | 1992-04-28 |
| 5093778 | Integrated single structure branch prediction cache | John G. Favor, David R. Stiles, Walstein Bennett Smith, III | 1992-03-03 |
| 4862346 | Index for a register file with update of addresses using simultaneously received current, change, test, and reload addresses | Lawrence F. Wagner, Jr., Wayne Burleson, Robert D. Hemming, John P. Guadagna | 1989-08-29 |
| 4852038 | Logarithmic calculating apparatus | Lawrence F. Wagner, Jr., Wayne Burleson | 1989-07-25 |