Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Larry Widigen — 20 Patents

AMD: 16 patents #727 of 9,280Top 8%
NANexgen Ag: 4 patents #1 of 14Top 8%
Salinas, CA: #13 of 367 inventorsTop 4%
California: #29,208 of 386,348 inventorsTop 8%
Overall (All Time): #214,803 of 4,157,543Top 6%
20 Patents All Time
Larry Widigen has been granted 20 US patents while listed as an inventor at AMD. The first was granted in 1995 and the most recent in December 2003. Larry Widigen ranks #214,803 of 4,157,543 US inventors in our database (top 5.2%). Patent records list Larry Widigen in Salinas, CA, US.

Issued Patents All Time

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6671798 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2003-12-30 $4,545,000
6360318 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2002-03-19 $4,163,000
6282639 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2001-08-28 $6,206,000
6195745 Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 2001-02-27 $7,317,000
6108777 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 2000-08-22 $6,781,000
6041396 Segment descriptor cache addressed by part of the physical address of the desired descriptor 2000-03-21 $7,844,000
5923579 Optimized binary adder and comparator having an implicit constant for an input Elliot A. Sowadsky 1999-07-13 $2,323,000
5919256 Operand cache addressed by the instruction address for reducing latency of read instruction Elliot A. Sowadsky 1999-07-06 $3,020,000
5822786 Apparatus and method for determining if an operand lies within an expand up or expand down segment Elliot A. Sowadsky 1998-10-13 $2,622,000
5815699 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 1998-09-29 $4,554,000
5802339 Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 1998-09-01 $2,453,000
5699279 Optimized binary adders and comparators for inputs having different widths Elliot A. Sowadsky 1997-12-16 $19,263,000
5675758 Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 1997-10-07 $8,877,000
5623614 Branch prediction cache with multiple entries for returns having multiple callers Korbin S. Van Dyke, David L. Puziol 1997-04-22 $14,872,000
5590351 Superscalar execution unit for sequential instruction pointer updates and segment limit checks Elliot A. Sowadsky, David L. Puziol, Korbin S. Van Dyke 1996-12-31 $7,393,000
5583806 Optimized binary adder for concurrently generating effective and intermediate addresses William A. Stutz 1996-12-10 $6,328,000
5517440 Optimized binary adders and comparators for inputs having different widths Elliot A. Sowadsky 1996-05-14
5454117 Configurable branch prediction for a processor performing speculative execution David L. Puziol, Korbin S. Van Dyke, Len Shar, Walstein Bennett Smith, III 1995-09-26 $9,289,000
5418736 Optimized binary adders and comparators for inputs having different widths Elliot A. Sowadsky 1995-05-23
5394351 Optimized binary adder and comparator having an implicit constant for an input Elliot A. Sowadsky 1995-02-28