Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11379388 | Credit scheme for multi-queue memory controllers | Shriram Ravichandran | 2022-07-05 |
| 11222685 | Refresh management for DRAM | Kevin M. Brandl, Jing Wang, Guanhao Shen | 2022-01-11 |
| 11200106 | Data integrity for persistent memory systems and the like | James R. Magro, Kevin M. Lepak, Vilas Sridharan | 2021-12-14 |
| 11194382 | Speculative exit from power down mode of a dynamic random access memory rank | — | 2021-12-07 |
| 11137941 | Command replay for non-volatile dual inline memory modules | Jing Wang, James R. Magro | 2021-10-05 |
| 11099786 | Signaling for heterogeneous memory systems | James R. Magro | 2021-08-24 |
| 10846253 | Dynamic page state aware scheduling of read/write burst transactions | Guanhao Shen, Ravindra N. Bhargava | 2020-11-24 |
| 10684969 | Command arbitration for high speed memory interfaces | James R. Magro, Jackson Peng, Hideki Kanayama | 2020-06-16 |
| 10535393 | Configuring dynamic random access memory refreshes for systems having multiple ranks of memory | — | 2020-01-14 |
| 10503670 | Dynamic per-bank and all-bank refresh | Guanhao Shen, Ravindra N. Bhargava, James R. Magro, Jing Wang | 2019-12-10 |
| 10403333 | Memory controller with flexible address decoding | Kevin M. Brandl, Thomas H. Hamilton, Hideki Kanayama, James R. Magro, Guanhao Shen +1 more | 2019-09-03 |
| 10402120 | Memory controller arbiter with streak and read/write transaction management | — | 2019-09-03 |
| 10296230 | Scheduling memory requests with non-uniform latencies | James R. Magro | 2019-05-21 |
| 10275352 | Supporting responses for memory types with non-uniform latencies on same channel | James R. Magro | 2019-04-30 |
| 10198216 | Low power memory throttling | Kevin M. Brandl, James R. Magro | 2019-02-05 |
| 10037150 | Memory controller with virtual controller mode | James R. Magro | 2018-07-31 |
| 9899074 | Fine granularity refresh | — | 2018-02-20 |
| 9576637 | Fine granularity refresh | — | 2017-02-21 |
| 7610540 | Method for generating, from a test cube set, a generator configured to generate a test pattern | Seongmoon Wang, Wenlong Wei, Srimat Chakradhar | 2009-10-27 |
| 7610539 | Method and apparatus for testing logic circuit designs | Seongmoon Wang, Wenlong Wei, Srimat Chakradhar | 2009-10-27 |
| 7610527 | Test output compaction with improved blocking of unknown values | Seongmoon Wang, Srimat Chakradhar | 2009-10-27 |
| 7577540 | Re-configurable embedded core test protocol for system-on-chips (SOC) and circuit boards | Seongmoon Wang, Srimat Chakradhar | 2009-08-18 |
| 7484151 | Method and apparatus for testing logic circuit designs | Seongmoon Wang, Wenlong Wei, Srimat Chakradhar | 2009-01-27 |
| 7302626 | Test pattern compression with pattern-independent design-independent seed compression | Seongmoon Wang, Srimat Chakradhar | 2007-11-27 |