Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6378023 | Interrupt descriptor cache for a microprocessor | Brian C. Barnes | 2002-04-23 |
| 6351801 | Program counter update mechanism | Scott White, Michael D. Goddard | 2002-02-26 |
| 6328343 | Riser dog screw with fail safe mechanism | Stanley Hosie | 2001-12-11 |
| 6247107 | Chipset configured to perform data-directed prefetching | — | 2001-06-12 |
| 6230259 | Transparent extended state save | Uwe Kranich | 2001-05-08 |
| 6185675 | Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks | Uwe Kranich | 2001-02-06 |
| 6175906 | Mechanism for fast revalidation of virtual tags | — | 2001-01-16 |
| 6157996 | Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space | Uwe Kranich | 2000-12-05 |
| 6154818 | System and method of controlling access to privilege partitioned address space for a model specific register file | — | 2000-11-28 |
| 6151662 | Data transaction typing for improved caching and prefetching characteristics | Brian D. McMinn, Stephan G. Meier, James K. Pickett | 2000-11-21 |
| 6076605 | Horizontal tree block for subsea wellhead and completion method | Robert O. Lilley, Stephen P. Fenton, Peter A. Scott, Walter J. Lacey | 2000-06-20 |
| 6076156 | Instruction redefinition using model specific registers | James K. Pickett | 2000-06-13 |
| 6055650 | Processor configured to detect program phase changes and to adapt thereto | — | 2000-04-25 |
| 6035386 | Program counter update mechanism | Scott White, Michael D. Goddard | 2000-03-07 |
| 6014739 | Increasing general registers in X86 processors | — | 2000-01-11 |
| 6009512 | Mechanism for forwarding operands based on predicated instructions | — | 1999-12-28 |
| 5948093 | Microprocessor including an interrupt polling unit configured to poll external devices for interrupts when said microprocessor is in a task switch state | Scott E. Swanstrom, Steven L. Belt | 1999-09-07 |
| 5944816 | Microprocessor configured to execute multiple threads including interrupt service routines | Drew J. Dutton, Brian C. Barnes | 1999-08-31 |
| 5944841 | Microprocessor with built-in instruction tracing capability | — | 1999-08-31 |
| 5918056 | Segmentation suspend mode for real-time interrupt support | — | 1999-06-29 |
| 5835511 | Method and mechanism for checking integrity of byte enable signals | — | 1998-11-10 |
| 5822778 | Microprocessor and method of using a segment override prefix instruction field to expand the register file | Drew J. Dutton | 1998-10-13 |
| 5819080 | Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor | Drew J. Dutton | 1998-10-06 |
| 5805853 | Superscalar microprocessor including flag operand renaming and forwarding apparatus | Scott White, Michael D. Goddard | 1998-09-08 |
| 5799162 | Program counter update mechanism | Scott White, Michael D. Goddard | 1998-08-25 |