| 11785332 |
Production shot design system |
Stephen Beres |
2023-10-10 |
| 11252333 |
Production shot design system |
Stephen Beres |
2022-02-15 |
| 7890740 |
Processor comprising a first and a second mode of operation and method of operating the same |
— |
2011-02-15 |
| 7689809 |
Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system |
— |
2010-03-30 |
| 7012604 |
System architecture for high speed ray tracing |
David S. Christie |
2006-03-14 |
| 6651163 |
Exception handling with reduced overhead in a multithreaded multiprocessing system |
David S. Christie |
2003-11-18 |
| 6574725 |
Method and mechanism for speculatively executing threads of instructions |
David S. Christie |
2003-06-03 |
| 6456891 |
System and method for transparent handling of extended register states |
David S. Christie |
2002-09-24 |
| 6230259 |
Transparent extended state save |
David S. Christie |
2001-05-08 |
| 6185675 |
Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks |
David S. Christie |
2001-02-06 |
| 6157996 |
Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space |
David S. Christie |
2000-12-05 |
| 5900022 |
Apparatus and method for reducing the cache miss penalty in a virtual addressed memory system by using a speculative address generator and an accurate address generator |
— |
1999-05-04 |
| 5850534 |
Method and apparatus for reducing cache snooping overhead in a multilevel cache system |
— |
1998-12-15 |
| 5761443 |
Computer system employing a bus conversion bridge for interfacing a master device residing on a multiplexed peripheral bus to a slave device residing on a split-address, split-data multiplexed peripheral bus |
— |
1998-06-02 |
| 5761709 |
Write cache for servicing write requests within a predetermined address range |
— |
1998-06-02 |
| 5752263 |
Apparatus and method for reducing read miss latency by predicting sequential instruction read-aheads |
— |
1998-05-12 |
| 5546560 |
Device and method for reducing bus activity in a computer system having multiple bus-masters |
— |
1996-08-13 |
| 5524225 |
Cache system and method for providing software controlled writeback |
— |
1996-06-04 |
