CJ

Chun Jiang

AM AMD: 10 patents #1,209 of 9,279Top 15%
LS Lattice Semiconductor: 6 patents #84 of 544Top 20%
VT Vlsi Technology: 5 patents #103 of 594Top 20%
NL Ningbo Liyang New Material Company Limited: 1 patents #4 of 5Top 80%
IN Inventec: 1 patents #521 of 1,270Top 45%
Nsk: 1 patents #937 of 1,559Top 65%
BC Beijing Bytedance Network Technology Co.: 1 patents #308 of 765Top 45%
📍 Ningbo City, CA: #10 of 43 inventorsTop 25%
Overall (All Time): #67,081 of 4,157,543Top 2%
44
Patents All Time

Issued Patents All Time

Showing 26–44 of 44 patents

Patent #TitleCo-InventorsDate
6628961 Device and a method for connecting a mobile phone handset to an external keyboard Martin Ho 2003-09-30
6600188 EEPROM with a neutralized doping at tunnel window edge Sunil Mehta 2003-07-29
6593632 Interconnect methodology employing a low dielectric constant etch stop layer Steven C. Avanzino, Minh Van Ngo, Angela T. Hui, Hamid Partovi 2003-07-15
6545313 EEPROM tunnel window for program injection via P+ contacted inversion Robert H. Tu, Sunil Mehta 2003-04-08
6455375 Eeprom tunnel window for program injection via P+ contacted inversion Robert H. Tu, Sunil Mehta 2002-09-24
6440839 Selective air gap insulation Hamid Partovi, Bill Liu 2002-08-27
6307541 Method and system for inputting chinese-characters through virtual keyboards to data processor Chi-Yu Ho, Chang Wang 2001-10-23
6166558 Method for measuring gate length and drain/source gate overlap Wei Long, Zicheng Gary Ling, Yowjuang W. Liu 2000-12-26
6137126 Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer Steven C. Avanzino, Minh Van Ngo, Angela T. Hui, Hamid Partovi 2000-10-24
6110219 Model for taking into account gate resistance induced propagation delay 2000-08-29
6099576 System for designing and manufacturing CMOS inverters by estimating gate RC delay 2000-08-08
6069485 C-V method to extract lateral channel doping profiles of MOSFETs Wei Long, Yowjuang W. Liu 2000-05-30
5986477 Method and system for providing an interconnect layout to reduce delays in logic circuits Linda Milor 1999-11-16
5925914 Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance David Wu 1999-07-20
5714785 Asymmetric drain/source layout for robust electrostatic discharge protection 1998-02-03
5712200 N-well resistor as a ballast resistor for output MOSFET 1998-01-27
5637902 N-well resistor as a ballast resistor for output MOSFET 1997-06-10
5587665 Testing hot carrier induced degradation to fall and rise time of CMOS inverter circuits 1996-12-24
5339270 AC drain voltage charging source for PROM devices 1994-08-16