Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10514973 | Memory and logic lifetime simulation systems and methods | Taizhi Liu, Chang-Chih Chen | 2019-12-24 |
| 10303541 | Technologies for estimating remaining life of integrated circuits using on-chip memory | Woongrae Kim, Taizhi Liu | 2019-05-28 |
| 6448098 | Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer | — | 2002-09-10 |
| 6054721 | Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer | — | 2000-04-25 |
| 5986477 | Method and system for providing an interconnect layout to reduce delays in logic circuits | Chun Jiang | 1999-11-16 |
| 5886909 | Defect diagnosis using simulation for IC yield improvement | Yeng-Kaung Peng, Khoi A. Phan, David A. Steele | 1999-03-23 |