Issued Patents All Time
Showing 51–75 of 105 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7684232 | Memory cell for storing a data bit value despite atomic radiation | — | 2010-03-23 |
| 7619486 | Method for detecting and compensating for temperature effects | — | 2009-11-17 |
| 7539926 | Method of correcting errors stored in a memory array | — | 2009-05-26 |
| 7535213 | Method and system for prediction of atmospheric upsets in an integrated circuit | — | 2009-05-19 |
| 7525362 | Circuit for and method of preventing an error in a flip-flop | Tan C. Hoang | 2009-04-28 |
| 7505542 | Low jitter digital frequency synthesizer with frequency modulation capabilities | — | 2009-03-17 |
| 7452765 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Martin L. Voogel, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart +3 more | 2008-11-18 |
| 7437633 | Duty cycle characterization and adjustment | Yiding Wu | 2008-10-14 |
| 7408381 | Circuit for and method of implementing a plurality of circuits on a programmable logic device | Saar Drimer, Jason J. Moore | 2008-08-05 |
| 7403051 | Determining voltage level validity for a power-on reset condition | — | 2008-07-22 |
| 7291923 | Tapered signal lines | Peter H. Alfke | 2007-11-06 |
| 7268581 | FPGA with time-multiplexed interconnect | Stephen M. Trimberger | 2007-09-11 |
| 7254157 | Method and apparatus for generating a phase locked spread spectrum clock signal | Patrick J. Crotty | 2007-08-07 |
| 7240320 | Routing with derivative frame awareness to minimize device programming time and test cost | Stephen M. Trimberger, Bernard J. New | 2007-07-03 |
| 7218670 | Method of measuring the performance of a transceiver in a programmable logic device | Saar Drimer | 2007-05-15 |
| 7142823 | Low jitter digital frequency synthesizer and control thereof | John D. Logue, Wei Guang Lu | 2006-11-28 |
| 7143329 | FPGA configuration memory with built-in error correction mechanism | Stephen M. Trimberger, Derek R. Curd | 2006-11-28 |
| 7110446 | Method and apparatus for reducing effect of jitter | Robert E. Eccles | 2006-09-19 |
| 7088172 | Configurable voltage bias circuit for controlling buffer delays | Patrick J. Crotty | 2006-08-08 |
| 7062692 | Duty cycle characterization and adjustment | — | 2006-06-13 |
| 7003679 | System and method for storing a charging algorithm and charging methodology associated with a battery and selectively connecting a critical circuit to a battery voltage pin | John S. Elward | 2006-02-21 |
| 6982451 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Martin L. Voogel, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart +3 more | 2006-01-03 |
| 6963218 | Bi-directional interface and communication link | Mark A. Alexander | 2005-11-08 |
| 6946870 | Control of simultaneous switch noise from multiple outputs | — | 2005-09-20 |
| 6914804 | Memory cells enhanced for resistance to single event upset | — | 2005-07-05 |