Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 7143376 | Method and apparatus for design verification with equivalency check | — | 2006-11-28 | $3,263,000 |
| 7124382 | Method and apparatus for rule file generation | Mark B. Roberts | 2006-10-17 | $13,661,000 |
| 7110446 | Method and apparatus for reducing effect of jitter | Austin H. Lesea | 2006-09-19 | $3,343,000 |
| 4678940 | TTL compatible merged bipolar/CMOS output buffer circuits | Nader Vasseghi, Donald G. Goddard | 1987-07-07 | $5,811,000 |