Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10423354 | Selective data copying between memory modules | Philip J. Rogers, Benjamin T. Sander, Gongxian Jeffrey Cheng | 2019-09-24 |
| 10365824 | Silent active page migration faults | Wade K. Smith | 2019-07-30 |
| 10339068 | Fully virtualized TLBs | Wade K. Smith | 2019-07-02 |
| 10324860 | Memory heaps in a memory model for a unified computing system | Kevin Normoyle, Mark Hummel | 2019-06-18 |
| 10223280 | Input/output memory map unit and northbridge | Vydhyanathan Kalyanasundharam, Yaniv Adiri, Philip Ng, Maggie Chan, Vincent Cueva +4 more | 2019-03-05 |
| 10209991 | Instruction set and micro-architecture supporting asynchronous memory access | Meenakshi Sundaram Bhaskaran, Elliot H. Mednick, David A. Roberts, Amin Farmahini-Farahani | 2019-02-19 |
| 10162765 | Routing direct memory access requests in a virtualized computing environment | Andrew G. Kegel | 2018-12-25 |
| 10152434 | Efficient arbitration for memory accesses | Rostyslav Kyrychynskyi, Kostantinos Danny Christidis, Mark Fowler, Michael Mantor, Robert Scott Hartog | 2018-12-11 |
| 10025721 | Input/output memory map unit and northbridge | Vydhyanathan Kalyanasundharam, Philip Ng, Maggie Chan, Vincent Cueva, Jimshed Mirza +4 more | 2018-07-17 |
| 9965392 | Managing coherent memory between an accelerated processing device and a central processing unit | Kevin Normoyle, Mark Hummel | 2018-05-08 |
| 9959593 | Memory controller having plurality of channels that provides simultaneous access to data when accessing unified graphics memory | Milivoje Aleksic, Raymond Li, Danny H. M. Cheng, Carl K. Mizuyabu | 2018-05-01 |
| 9910788 | Cache access statistics accumulation for cache line replacement selection | Philip J. Rogers, Benjamin T. Sander | 2018-03-06 |
| 9734549 | Memory device for providing data in a graphics system and method and apparatus thereof | Milivoje Aleksic, Raymond Li, Danny H. M. Cheng, Carl K. Mizuyabu | 2017-08-15 |
| 9448930 | Memory heaps in a memory model for a unified computing system | Kevin Normoyle, Mark Hummel | 2016-09-20 |
| 9430391 | Managing coherent memory between an accelerated processing device and a central processing unit | Kevin Normoyle, Mark Hummel | 2016-08-30 |
| 9201682 | Virtualized device reset | Gongxian Jeffrey Cheng, Yinan Jiang | 2015-12-01 |
| 9152571 | All invalidate approach for memory management units | Andrew G. Kegel, Mark Hummel | 2015-10-06 |
| 9116809 | Memory heaps in a memory model for a unified computing system | Kevin Normoyle, Mark Hummel | 2015-08-25 |
| 9009419 | Shared memory space in a unified memory model | Kevin Normoyle, Mark Hummel, Mark Fowler | 2015-04-14 |
| 8984511 | Visibility ordering in a memory model for a unified computing system | Kevin Normoyle, Mark Hummel | 2015-03-17 |
| 8933947 | Reading a local memory of a processing unit | David Glen, Philip J. Rogers, Gordon Caruk, Gongxian Jeffrey Cheng, Mark Hummel +1 more | 2015-01-13 |
| 8935475 | Cache management for memory operations | Kevin Normoyle, Mark Hummel, Norman Rubin, Mark Fowler | 2015-01-13 |
| 8924617 | Memory device for providing data in a graphics system and method and apparatus therof | Milivoje Aleksic, Raymond Li, Danny H. M. Cheng, Carl K. Mizuyabu | 2014-12-30 |
| 8719464 | Efficient memory and resource management | Andrew G. Kegel, Mark Hummel, Phillip Ng | 2014-05-06 |
| 8656198 | Method and apparatus for memory power management | Alexander J. Branover, Maurice B. Steinman, James B. Fry | 2014-02-18 |