Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9182999 | Reintialization of a processing system from volatile memory upon resuming from a low-power state | Andrew W. Lueck, Krishna Sai Bernucho, Paul Kitchin, Ronald Perez, Sonu Arora | 2015-11-10 |
| 9075609 | Power controller, processor and method of power management | William L. Bircher | 2015-07-07 |
| 9043625 | Processor bridge power management | Maurice B. Steinman, Denis Foley, Ljubisa Bajic | 2015-05-26 |
| 9021209 | Cache flush based on idle prediction and probe activity level | Maurice B. Steinman | 2015-04-28 |
| 8966305 | Managing processor-state transitions | Maurice B. Steinman, John P. Petry | 2015-02-24 |
| 8959372 | Dynamic performance control of processing nodes | Maurice B. Steinman, William L. Bircher | 2015-02-17 |
| 8924758 | Method for SOC performance and power optimization | Maurice B. Steinman, Guhan Krishnan | 2014-12-30 |
| 8862920 | Power state management of an input/output servicing component of a processor system | Maurice B. Steinman | 2014-10-14 |
| 8862909 | System and method for determining a power estimate for an I/O controller based on monitored activity levels and adjusting power limit of processing units by comparing the power estimate with an assigned power limit for the I/O controller | Madhu Saravana Sibi Govindan, Guhan Krishnan, Hemant R. Mohapatra, Andrew W. Lueck | 2014-10-14 |
| 8832485 | Method and apparatus for cache control | Norman M. Hack, Maurice B. Steinman, John Kalamatianos, Jonathan Owen | 2014-09-09 |
| 8793512 | Method and apparatus for thermal control of processing nodes | Samuel D. Naffziger | 2014-07-29 |
| 8656198 | Method and apparatus for memory power management | Maurice B. Steinman, Anthony Asaro, James B. Fry | 2014-02-18 |
| 8589629 | Method for way allocation and way locking in a cache | Jonathan Owen, Guhan Krishnan, Carl Dietz, Douglas R. Beard, William Kurt Lewchuk | 2013-11-19 |
| 8566628 | North-bridge to south-bridge protocol for placing processor in low power state | Maurice B. Steinman, Ming L. So, Xiao Gang Zheng | 2013-10-22 |
| 8484498 | Method and apparatus for demand-based control of processing node performance | Maurice B. Steinman, William L. Bircher | 2013-07-09 |
| 8463973 | Mechanism for voltage regulator load line compensation using multiple voltage settings per operating state | Samuel D. Naffziger | 2013-06-11 |
| 8447994 | Altering performance of computational units heterogeneously according to performance sensitivity | Sebastien Nussbaum, John Kalamatianos | 2013-05-21 |
| 8443209 | Throttling computational units according to performance sensitivity | Sebastien Nussbaum, John Kalamatianos | 2013-05-14 |
| 8438416 | Function based dynamic power control | Andrej Kocev | 2013-05-07 |
| 8412971 | Method and apparatus for cache control | Norman M. Hack, Maurice B. Steinman, John Kalamatianos, Jonathan Owen | 2013-04-02 |
| 8291249 | Method and apparatus for transitioning devices between power states based on activity request frequency | Denis Rystsov, Maurice B. Steinman, Jonathan Owen, Denis Foley | 2012-10-16 |
| 8156362 | Hardware monitoring and decision making for transitioning in and out of low-power state | Frank P. Helms, Maurice B. Steinman | 2012-04-10 |
| 8112647 | Protocol for power state determination and demotion | Frank P. Helms, John P. Petry, Maurice B. Steinman | 2012-02-07 |
| 8112648 | Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state | Maurice B. Steinman, Denis Rystsov | 2012-02-07 |
| 8028185 | Protocol for transitioning in and out of zero-power state | Rajen S. Ramchandani | 2011-09-27 |