Issued Patents All Time
Showing 76–100 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6279099 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Robert Yung | 2001-08-21 |
| 6044206 | Out of order instruction processing using dual memory banks | — | 2000-03-28 |
| 6006312 | Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses | Ken Okin, Dale R. Greenley | 1999-12-21 |
| 5938756 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Robert Yung | 1999-08-17 |
| 5931945 | Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of the control lines based on the mask register bits | Robert Yung, Timothy J. Van Hook | 1999-08-03 |
| 5933157 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Robert Yung | 1999-08-03 |
| 5907485 | Method and apparatus for flow control in packet-switched computer system | William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Louis F. Coffin, III | 1999-05-25 |
| 5904732 | Dynamic priority switching of load and store buffers in superscalar processor | Dale R. Greenley | 1999-05-18 |
| 5842225 | Method and apparatus for implementing non-faulting load instruction | — | 1998-11-24 |
| 5802575 | Hit bit for indicating whether load buffer entries will hit a cache when they reach buffer head | Dale R. Greenley, Ming-Hsin Yeh, Greg Williams | 1998-09-01 |
| 5745729 | Methods and apparatuses for servicing load instructions | Dale R. Greenley, Ming-Hsin Yeh, Greg Williams | 1998-04-28 |
| 5737755 | System level mechanism for invalidating data stored in the external cache of a processor in a computer system | Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, Louis F. Coffin, III | 1998-04-07 |
| 5734874 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Robert Yung | 1998-03-31 |
| 5727219 | Virtual input/output processor utilizing an interrupt handler | Thomas L. Lyon, Sun Den Chen, William N. Joy, Charles E. Narad, Robert Yung | 1998-03-10 |
| 5706463 | Cache coherent computer system that minimizes invalidation and copyback operations | Zahir Ebrahim, Satyanarayana Nishtala, William Loo, Kevin Normoyle, Louis F. Coffin, III | 1998-01-06 |
| 5692197 | Method and apparatus for reducing power consumption in a computer network without sacrificing performance | Charles E. Narad, Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle +1 more | 1997-11-25 |
| 5657472 | Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor | William C. Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Louis F. Coffin, III +1 more | 1997-08-12 |
| 5634068 | Packet switched cache coherent multiprocessor system | Satyanarayana Nishtala, Zahir Ebrahim, William C. Van Loo, Kevin Normoyle, Louis F. Coffin, III | 1997-05-27 |
| 5546551 | Method and circuitry for saving and restoring status information in a pipelined computer | — | 1996-08-13 |
| 5276847 | Method for locking and unlocking a computer address | — | 1994-01-04 |
| 5265227 | Parallel protection checking in an address translation look-aside buffer | Shai Rotem | 1993-11-23 |
| 5241636 | Method for parallel instruction execution in a computer | — | 1993-08-31 |
| 5204828 | Bus apparatus having hold registers for parallel processing in a microprocessor | — | 1993-04-20 |
| 5157388 | Method and apparatus for graphics data interpolation | — | 1992-10-20 |
| 5155816 | Pipelined apparatus and method for controlled loading of floating point data in a microprocessor | — | 1992-10-13 |