Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6396504 | Graphical image data reformatting method and apparatus | Carlan Joseph Beheler, Jaijiv Prabhakaran | 2002-05-28 |
| 6385713 | Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements | — | 2002-05-07 |
| 6304961 | Computer system and method for fetching a next instruction | Kit S. Tam, Alfred Yeung, William N. Joy | 2001-10-16 |
| 6279099 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Leslie D. Kohn | 2001-08-21 |
| 6205538 | Instruction result labeling in a counterflow pipeline processor | — | 2001-03-20 |
| 6128721 | Temporary pipeline register file for a superpipelined superscalar processor | William N. Joy, Marc Tremblay | 2000-10-03 |
| 5996066 | Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions | — | 1999-11-30 |
| 5956747 | Processor having a plurality of pipelines and a mechanism for maintaining coherency among register values in the pipelines | Neil C. Wilhelm | 1999-09-21 |
| 5938756 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Leslie D. Kohn | 1999-08-17 |
| 5931945 | Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of the control lines based on the mask register bits | Leslie D. Kohn, Timothy J. Van Hook | 1999-08-03 |
| 5933157 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Leslie D. Kohn | 1999-08-03 |
| 5918245 | Microprocessor having a cache memory system using multi-level cache set prediction | — | 1999-06-29 |
| 5809324 | Multiple instruction dispatch system for pipelined microprocessor without branch breaks | — | 1998-09-15 |
| 5761472 | Interleaving block operations employing an instruction set capable of delaying block-store instructions related to outstanding block-load instructions in a computer system | Stephen K. Howell | 1998-06-02 |
| 5761475 | Computer processor having a register file with reduced read and/or write port bandwidth | Neil C. Wilhelm | 1998-06-02 |
| 5752271 | Method and apparatus for using double precision addressable registers for single precision data | — | 1998-05-12 |
| 5734874 | Central processing unit with integrated graphics functions | Timothy J. Van Hook, Leslie D. Kohn | 1998-03-31 |
| 5727219 | Virtual input/output processor utilizing an interrupt handler | Thomas L. Lyon, Sun Den Chen, William N. Joy, Leslie D. Kohn, Charles E. Narad | 1998-03-10 |
| 5721868 | Rapid register file access by limiting access to a selectable register subset | William N. Joy, Michael R. Allen, Marc Tremblay | 1998-02-24 |
| 5717896 | Method and apparatus for performing pipeline store instructions using a single cache access pipestage | Guillermo Maturana | 1998-02-10 |
| 5682493 | Scoreboard table for a counterflow pipeline processor with instruction packages and result packages | Robert F. Sproull | 1997-10-28 |
| 5592679 | Apparatus and method for distributed control in a processor architecture | — | 1997-01-07 |
| 5548739 | Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using address page crossing predictive annotations | — | 1996-08-20 |
| 5546554 | Apparatus for dynamic register management in a floating point unit | Greg Williams, Huoy-Ming Yeh | 1996-08-13 |
| 5392414 | Rapid data retrieval from data storage structures using prior access predictive annotations | — | 1995-02-21 |