Issued Patents All Time
Showing 26–50 of 198 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12125124 | Matrix transpose hardware acceleration | Kun Xu | 2024-10-22 |
| 12106222 | Neural network training under memory restraint | Sudipta Sengupta, Randy Renfu Huang, Vignesh Vivekraja | 2024-10-01 |
| 12099840 | Throughput increase for tensor operations | Xiaodan Tan, Paul Gilbert Meyer | 2024-09-24 |
| 12093806 | Static memory allocation for neural network inference | Jindrich Zejda, Jeffrey T. Huynh, Drazen Borkovic, Randy Renfu Huang, Richard John Heaton | 2024-09-17 |
| 12093801 | Neural network processing based on subgraph recognition | Richard John Heaton, Randy Renfu Huang | 2024-09-17 |
| 12073199 | Reducing computation in neural networks using self-modifying code | Vignesh Vivekraja, Randy Renfu Huang, Yu Zhou, Richard John Heaton | 2024-08-27 |
| 12067492 | Processing for multiple input data sets in a multi-layer neural network | Dana Michelle Vantrease, Thomas A. Volpe, Randy Renfu Huang | 2024-08-20 |
| 12056072 | Low latency memory notification | Patricio Kaplan | 2024-08-06 |
| 12045611 | Reconfigurable neural network processing based on subgraph recognition | Hongbin Zheng, Drazen Borkovic, Haichen Li | 2024-07-23 |
| 12045475 | Resizable scratchpad memory | Paul Gilbert Meyer, Patricio Kaplan, Sundeep Amirineni, Laura Sharpless, Akshay Balasubramanian | 2024-07-23 |
| 12026607 | Memory operation for systolic array | Jeffrey T. Huynh | 2024-07-02 |
| 12008469 | Acceleration of neural networks with stacks of convolutional layers | Thiam Khean Hah, Randy Renfu Huang, Richard John Heaton, Vignesh Vivekraja | 2024-06-11 |
| 12008466 | Processor with control flow | Randy Renfu Huang, Thomas A. Volpe | 2024-06-11 |
| 12008368 | Programmable compute engine having transpose operations | Xiaodan Tan, Paul Gilbert Meyer, Sheng Xu | 2024-06-11 |
| 12001352 | Transaction ordering based on target address | Rashika Kheria, Se Wang Oh, Guy Nakibly | 2024-06-04 |
| 11983128 | Multidimensional and multiblock tensorized direct memory access descriptors | Kun Xu, Ilya Minkin, Mohammad El-Shabani, Raymond Scott Whiteside, Uday Shilton Udayaselvam | 2024-05-14 |
| 11960566 | Reducing computations for data including padding | Dana Michelle Vantrease | 2024-04-16 |
| 11960997 | Circuit architecture with biased randomization | Randy Renfu Huang | 2024-04-16 |
| 11941528 | Neural network training in a distributed system | Vignesh Vivekraja, Thiam Khean Hah, Randy Renfu Huang, Richard John Heaton | 2024-03-26 |
| 11880682 | Systolic array with efficient input reduction and extended array performance | Paul Gilbert Meyer, Thomas A. Volpe, Joshua W. Bowman, Nishith Desai, Thomas Elmer | 2024-01-23 |
| 11880289 | Auto-detection of interconnect hangs in integrated circuits | Noga Smith, Saar Gross | 2024-01-23 |
| 11874785 | Memory access operation in distributed computing system | Patricio Kaplan | 2024-01-16 |
| 11875247 | Input batching with serial dynamic memory access | Richard John Heaton | 2024-01-16 |
| 11870761 | Hardware security accelerator | Nafea Bshara, Leah Shalev, Erez Izenberg | 2024-01-09 |
| 11868878 | Executing sublayers of a fully-connected layer | Randy Renfu Huang | 2024-01-09 |