Issued Patents All Time
Showing 51–75 of 198 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11868895 | Dynamic processing element array expansion | Randy Renfu Huang, Richard John Heaton | 2024-01-09 |
| 11868875 | Data selection circuit | Randy Renfu Huang, Jeffrey T. Huynh, Sundeep Amirineni | 2024-01-09 |
| 11868872 | Direct memory access operation for neural network accelerator | Ilya Minkin, Kun Xu | 2024-01-09 |
| 11841792 | Instructions with multiple memory access modes | — | 2023-12-12 |
| 11816559 | Dilated convolution using systolic array | Jeffrey T. Huynh | 2023-11-14 |
| 11803736 | Fine-grained sparsity computations in systolic array | Paul Gilbert Meyer, Thiam Khean Hah, Randy Renfu Huang, Vignesh Vivekraja | 2023-10-31 |
| 11797853 | Processing for multiple input data sets | Dana Michelle Vantrease, Thomas A. Volpe, Randy Renfu Huang | 2023-10-24 |
| 11782706 | Reconfigurable neural network processing based on subgraph recognition | Hongbin Zheng, Drazen Borkovic, Haichen Li | 2023-10-10 |
| 11775430 | Memory access for multiple circuit components | Sundeep Amirineni, Akshay Balasubramanian, Eyal Freund | 2023-10-03 |
| 11775268 | Color selection schemes for storage allocation | Preston Pengra Briggs, III, Robert Geva | 2023-10-03 |
| 11741350 | Efficient utilization of processing element array | Jeffrey T. Huynh, Hongbin Zheng, Yizhi Liu, Animesh Jain, Yida Wang +5 more | 2023-08-29 |
| 11741345 | Multi-memory on-chip computational network | Randy Renfu Huang | 2023-08-29 |
| 11720523 | Performing concurrent operations in a processing element | Dana Michelle Vantrease | 2023-08-08 |
| 11714992 | Neural network processing based on subgraph recognition | Richard John Heaton, Randy Renfu Huang | 2023-08-01 |
| 11704211 | Error avoidance in memory device | Patricio Kaplan, Brian Robert Silver | 2023-07-18 |
| 11687761 | Improper neural network input detection and handling | Randy Renfu Huang, Richard John Heaton, Andrea Olgiati | 2023-06-27 |
| 11676021 | Multi-model training pipeline in distributed systems | Patricio Kaplan | 2023-06-13 |
| 11645075 | Program flow classification | Barak Wasserstrom, Adi Habusha, Erez Sabbag | 2023-05-09 |
| 11636569 | Matrix transpose hardware acceleration | Kun Xu | 2023-04-25 |
| 11625453 | Using shared data bus to support systolic array tiling | Paul Gilbert Meyer | 2023-04-11 |
| 11625269 | Scheduling for locality of reference to memory | Robert Geva, Taylor Goodhart, Preston Pengra Briggs, III | 2023-04-11 |
| 11610128 | Neural network training under memory restraint | Sudipta Sengupta, Randy Renfu Huang, Vignesh Vivekraja | 2023-03-21 |
| 11568238 | Dynamic processing element array expansion | Randy Renfu Huang, Richard John Heaton | 2023-01-31 |
| 11567778 | Neural network operation reordering for parallel execution | Jeffrey T. Huynh, Drazen Borkovic, Jindrich Zejda, Randy Renfu Huang | 2023-01-31 |
| 11550736 | Tensorized direct memory access descriptors | Kun Xu, Ilya Minkin, Mohammad El-Shabani, Raymond Scott Whiteside, Uday Shilton Udayaselvam | 2023-01-10 |