Issued Patents All Time
Showing 51–64 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8053808 | Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device | Yi Su, Anup Bhalla, Wei-Chuan Wang, Ji Pan | 2011-11-08 |
| 7952144 | Integration of a sense FET into a discrete power MOSFET | Yi Su, Anup Bhalla | 2011-05-31 |
| 7943989 | Nano-tube MOSFET technology and devices | Hamza Yilmaz, Lingpeng Guan, Anup Bhalla, Wilson Ma, Moses Ho +1 more | 2011-05-17 |
| 7902604 | Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection | Yi Su, Anup Bhalla | 2011-03-08 |
| 7825431 | Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection | Anup Bhalla, Xiaobin Wang, Wei-Chuan Wang, Yi Su | 2010-11-02 |
| 7799646 | Integration of a sense FET into a discrete power MOSFET | Yi Su, Anup Bhalla | 2010-09-21 |
| 7659570 | Power MOSFET device structure for high frequency applications | Anup Bhalla, Tiesheng Li, Sik Lui | 2010-02-09 |
| 7535021 | Calibration technique for measuring gate resistance of power MOS gate device at water level | Anup Bhalla, Sik Lui | 2009-05-19 |
| 7504676 | Planar split-gate high-performance MOSFET structure and manufacturing method | Anup Bhalla, Francois Hebert | 2009-03-17 |
| 7436022 | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout | Anup Bhalla, Sik Lui | 2008-10-14 |
| 6107160 | MOSFET having buried shield plate for reduced gate/drain capacitance | Francois Hebert | 2000-08-22 |
| 5929481 | High density trench DMOS transistor with trench bottom implant | Fwu-Iuan Hshieh, Brian H. Floyd, Mike F. Chang, Danny Chi Nim | 1999-07-27 |
| 5912490 | MOSFET having buried shield plate for reduced gate/drain capacitance | Francois Hebert | 1999-06-15 |
| 5898198 | RF power device having voltage controlled linearity | Francois Herbert, James R. Parker, Howard D. Bartlow | 1999-04-27 |