Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
ME

Mark Elston — 19 Patents

ADAdvantest: 8 patents #114 of 1,193Top 10%
ACAdvantest America R&D Center: 6 patents #1 of 8Top 15%
W2W2Bi: 5 patents #7 of 15Top 50%
Salinas, CA: #15 of 367 inventorsTop 5%
California: #31,067 of 386,348 inventorsTop 9%
Overall (All Time): #229,345 of 4,157,543Top 6%
19 Patents All Time
Mark Elston has been granted 19 US patents while listed as an inventor at Advantest. The first was granted in 2007 and the most recent in June 2020. Mark Elston ranks #229,345 of 4,157,543 US inventors in our database (top 5.5%). Patent records list Mark Elston in Salinas, CA, US.

Patents per Year

Patents granted per year, 2007 to 2020Bar chart with a peak of 5 patents in 2007.peak 52007: 5 patents20072008: 2 patents20082009: 1 patents20092011: 1 patents20112012: 2 patents20122016: 1 patents20162017: 2 patents20172018: 1 patents20182019: 1 patents20192020: 3 patents2020

Issued Patents All Time

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10701571 Automated validation and calibration portable test systems and methods Dinesh Doshi, Vipul Jain, Amit Kucheriya, Derek Diperna, Liqun Liu +1 more 2020-06-30
10681570 Automated configurable portable test systems and methods Dinesh Doshi, Vipul Jain, Derek Diperna, Amit Kucheriya, Liqun Liu +1 more 2020-06-09
10548033 Local portable test systems and methods Dinesh Doshi, Amit Kucheriya, Derek Diperna, Vipul Jain, Liqun Liu +1 more 2020-01-28
10251079 Cloud-based services for management of cell-based test systems Dinesh Doshi, Amit Kucheriya, Liqun Liu, Vipul Jain, Derek Diperna +1 more 2019-04-02
10158552 Device profile-driven automation for cell-based test systems Dinesh Doshi, Derek Diperna, Vipul Jain, Liqun Liu, Amit Kucheriya +1 more 2018-12-18
9785526 Automated generation of a test class pre-header from an interactive graphical user interface Ankan Pramanick, Leon Chen, Chandra Pinjala 2017-10-10
9785542 Implementing edit and update functionality within a development environment used to compile test plans for automated semiconductor device testing Leon Chen, Harsanjeet Singh, Hironori Maeda, Ankan Pramanick, Youbi Katsu 2017-10-10
9274911 Using shared pins in a concurrent test execution environment Harsanjeet Singh, Ankan Pramanick, Leon Chen, Hironori Maeda, Chandra Pinjala +1 more 2016-03-01 $66,000
8255198 Method and structure to develop a test program for semiconductor integrated circuits Ramachandran Krishnaswamy, Harsanjeet Singh, Ankan Pramanick, Leon Chen, Toshiaki Adachi +1 more 2012-08-28 $47,000
8214800 Compact representation of vendor hardware module revisions in an open architecture test system Ankan Pramanick, Toshiaki Adachi 2012-07-03 $90,000
8082541 Method and system for performing installation and configuration management of tester instrument modules Ankan Pramanick, Jim Hanrahan, Toshiaki Adachi, Leon Chen 2011-12-20 $32,000
7543200 Method and system for scheduling tests in a parallel test system Ankan Pramanick, Toshiaki Adachi 2009-06-02 $75,000
7437261 Method and apparatus for testing integrated circuits Ankan Pramanick, Leon Chen, Robert Sauer 2008-10-14 $77,000
7430486 Datalog support in a modular test system Ankan Pramanick 2008-09-30 $357,000
7210087 Method and system for simulating a modular test system Conrad Mukai, Ankan Pramanick, Toshiaki Adachi, Leon Chen 2007-04-24 $42,000
7209851 Method and structure to develop a test program for semiconductor integrated circuits Harsanjeet Singh, Ankan Pramanick, Yoshifumi Tahara, Toshiaki Adachi 2007-04-24 $42,000
7197417 Method and structure to develop a test program for semiconductor integrated circuits Ankan Pramanick, Ramachandran Krishnaswamy, Toshiaki Adachi 2007-03-27 $55,000
7197416 Supporting calibration and diagnostics in an open architecture test system Toshiaki Adachi, Ankan Pramanick 2007-03-27 $55,000
7184917 Method and system for controlling interchangeable components in a modular test system Ankan Pramanick, Toshiaki Adachi 2007-02-27 $75,000