GL

Geraldine Tsui Yee Lin

A- A-Sat: 3 patents #16 of 49Top 35%
UP Utac Headquarters Pte.: 1 patents #56 of 101Top 60%
UL Utac Hong Kong Limited: 1 patents #10 of 14Top 75%
📍 Tseung Kwan O, CN: #23 of 213 inventorsTop 15%
Overall (All Time): #851,040 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
9520306 Method of fabricating an integrated circuit (IC) package having a plurality of spaced apart pad portion Walter de Munnik, Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan +1 more 2016-12-13
8330270 Integrated circuit package having a plurality of spaced apart pad portions Walter de Munnik, Kin Pui Kwan, Wing Him Lau, Kwok Cheung Tsang, Chun Ho Fan +1 more 2012-12-11
7732914 Cavity-type integrated circuit package Neil McLellan, Katherine Wagenhoffer, Mohan Kirloskar 2010-06-08
7411289 Integrated circuit package with partially exposed contact pads and process for fabricating the same Neil McLellan, Chun Ho Fan, Mohan Kirloskar, Ed A. Varga 2008-08-12
7091581 Integrated circuit package and process for fabricating the same Neil McLellan, Chun Ho Fan, Mohan Kirloskar, Ed A. Varga 2006-08-15
6903304 Process for dressing molded array package saw blade Neil McLellan, Chun Ho Fan, John Ping Sheung Lau 2005-06-07