Issued Patents 2025
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426299 | Fin shaping and integrated circuit structures resulting therefrom | Szuya S. Liao, Rahul Pandey, Anupama Bowonder, Pratik A. Patel | 2025-09-23 |
| 12349420 | Device, method and system to provide a stressed channel of a transistor | Stephen M. Cea, Tahir Ghani, Anand S. Murthy | 2025-07-01 |
| 12336278 | Gate-all-around integrated circuit structures having high mobility | Roza Kotlyar, Stephen M. Cea, Biswajeet Guha, Dax M. Crum, Tahir Ghani | 2025-06-17 |
| 12317590 | Substrate-free integrated circuit structures | Biswajeet Guha, Brian J. Greene, Avyaya Jayanthinarasimham, Ayan Kar, Benjamin Orr +9 more | 2025-05-27 |
| 12310044 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea +1 more | 2025-05-20 |
| 12288813 | Gate-all-around integrated circuit structures having insulator fin on insulator substrate | Aaron D. Lilak, Cory E. Weber, Willy Rachmady, Varun MISHRA | 2025-04-29 |
| 12288807 | Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly | Aaron D. Lilak, Willy Rachmady, Harold W. Kennel, Tahir Ghani | 2025-04-29 |
| 12288810 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Aaron D. Lilak, Kimin Jun | 2025-04-29 |
| 12255137 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more | 2025-03-18 |
| 12224326 | Contact architecture for capacitance reduction and satisfactory contact resistance | Pratik A. Patel, Ralph T. Troeger, Szuya S. Liao | 2025-02-11 |
| 12199098 | Fin doping and integrated circuit structures resulting therefrom | Aaron D. Lilak, Cory E. Weber, Stephen M. Cea, Leonard C. Pipes, Seahee Hwangbo +3 more | 2025-01-14 |