Issued Patents 2024
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11948839 | Power reduction in finFET structures | Kuo-Cheng Ching, Chih-Hao Wang | 2024-04-02 |
| 11935921 | Dielectric structures for semiconductor devices | Kuo-Cheng Ching, Chih-Hao Wang | 2024-03-19 |
| 11923457 | FinFET structure with fin top hard mask and method of forming the same | Che-Yu Yang, Kai-Chieh Yang, Ching-Wei Tsai | 2024-03-05 |
| 11923361 | Semiconductor device with isolation structure | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang | 2024-03-05 |
| 11916072 | Gate isolation structure | Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Chih-Hao Wang | 2024-02-27 |
| 11916128 | Metal oxide interlayer structure for nFET and pFET | Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Chih-Hao Wang | 2024-02-27 |
| 11916110 | Semiconductor device having nanosheet transistor and methods of fabrication thereof | Chih-Ching Wang, Wei-Yang Lee, Ming-Chang Wen, Jo-Tzu HUNG, Wen-Hsing Hsieh | 2024-02-27 |
| 11908919 | Multi-gate devices with multi-layer inner spacers and fabrication methods thereof | Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh, Chung-Wei Wu, Zhiqiang Wu | 2024-02-20 |
| 11908942 | Transistors having nanostructures | Cheng-Ting Chung, Ching-Wei Tsai | 2024-02-20 |
| 11901456 | FinFET devices with a backside power rail and a backside self-aligned via disposed between dielectric fins | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang | 2024-02-13 |
| 11901428 | Semiconductor device with backside gate isolation structure and method for forming the same | Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Lo-Heng Chang, Cheng-Chi Chuang +1 more | 2024-02-13 |
| 11901365 | Finfet device and a method for fabricating the same | Wang-Chun Huang, Kai-Chieh Yang, Ching-Wei Tsai, Chih-Hao Wang | 2024-02-13 |
| 11894260 | Replacement material for backside gate cut feature | Wang-Chun Huang, Yu-Xuan Huang, Hou-Yu Chen, Chih-Hao Wang | 2024-02-06 |
| 11894460 | Semiconductor device having nanosheet transistor and methods of fabrication thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu +1 more | 2024-02-06 |
| 11894367 | Integrated circuit including dipole incorporation for threshold voltage tuning in transistors | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang +1 more | 2024-02-06 |
| 11876119 | Semiconductor device with gate isolation features and fabrication method of the same | Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Jia-Chuan You +2 more | 2024-01-16 |
| 11869955 | Integrated circuit with nanosheet transistors with robust gate oxide | Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu +1 more | 2024-01-09 |
| 11862734 | Self-aligned spacers for multi-gate devices and method of fabrication thereof | Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang | 2024-01-02 |
| 11862634 | Nanostructure with various widths | Hsiao-Han Liu, Chih-Hao Wang, Kuo-Cheng Chiang, Shi Ning Ju | 2024-01-02 |
| 11862700 | Semiconductor device structure including forksheet transistors and methods of forming the same | Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu +2 more | 2024-01-02 |
| 11862701 | Stacked multi-gate structure and methods of fabricating the same | Cheng-Ting Chung, Hou-Yu Chen | 2024-01-02 |
| 11862559 | Semiconductor structures and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang | 2024-01-02 |