Issued Patents 2024
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176391 | Semiconductor device structure having an isolation layer to isolate a conductive feature and a gate electrode layer | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuan-Lun Cheng, Kuo-Cheng Chiang +1 more | 2024-12-24 |
| 12170231 | Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai +3 more | 2024-12-17 |
| 12166100 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Chih-Hao Wang | 2024-12-10 |
| 12148750 | Work function design to increase density of nanosheet devices | Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Chung-Wei Hsu | 2024-11-19 |
| 12119391 | Fin-based semiconductor device structure including self-aligned contacts and method for forming the same | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang +2 more | 2024-10-15 |
| 12119266 | Semiconductor arrangement and method of manufacture | Kuo-Cheng Ching, Mao-Lin Huang, Chung-Wei Hsu | 2024-10-15 |
| 12107131 | Gate-all-around devices having self-aligned capping between channel and backside power rail | Chung-Wei Hsu, Mao-Lin Huang, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2024-10-01 |
| 12087771 | Multiple patterning gate scheme for nanosheet rule scaling | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang +2 more | 2024-09-10 |
| 12087772 | Nanosheet device architecture for cell-height scaling | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2024-09-10 |
| 12062693 | Semiconductor device structure and methods of forming the same | Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Chung-Wei Hsu, Chih-Hao Wang +1 more | 2024-08-13 |
| 12040191 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2024-07-16 |
| 12034006 | Input/output semiconductor devices | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang | 2024-07-09 |
| 12021132 | Gate patterning process for multi-gate devices | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang | 2024-06-25 |
| 11996298 | Reversed tone patterning method for dipole incorporation for multiple threshold voltages | Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang, Chih-Hao Wang | 2024-05-28 |
| 11996334 | Semiconductor device fabrication methods and structures thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2024-05-28 |
| 11961840 | Semiconductor device having nanosheet transistor and methods of fabrication thereof | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2024-04-16 |
| 11948987 | Self-aligned backside source contact structure | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2024-04-02 |
| 11942377 | Gate structure and patterning method | Mao-Lin Huang, Wei-Hao Wu, Kuo-Cheng Chiang | 2024-03-26 |
| 11915937 | Fluorine incorporation method for nanosheet | Hsin-Yi Lee, Mao-Lin Huang, Huang-Lin Chao, Chi On Chui | 2024-02-27 |
| 11901361 | Semiconductor structure and method for forming the same | Jia-Ni Yu, Kuo-Cheng Chiang, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang | 2024-02-13 |
| 11894367 | Integrated circuit including dipole incorporation for threshold voltage tuning in transistors | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2024-02-06 |
| 11894460 | Semiconductor device having nanosheet transistor and methods of fabrication thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2024-02-06 |
| 11869955 | Integrated circuit with nanosheet transistors with robust gate oxide | Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Chung-Wei Hsu, Chih-Hao Wang +1 more | 2024-01-09 |
| 11862700 | Semiconductor device structure including forksheet transistors and methods of forming the same | Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Chung-Wei Hsu, Chun-Fu Lu +2 more | 2024-01-02 |
| 11862633 | Work function design to increase density of nanosheet devices | Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Chung-Wei Hsu | 2024-01-02 |