Issued Patents 2024
Showing 26–50 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12087771 | Multiple patterning gate scheme for nanosheet rule scaling | Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu +2 more | 2024-09-10 |
| 12080646 | Semiconductor structures and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang | 2024-09-03 |
| 12074167 | Hybrid scheme for improved performance for P-type and N-type FinFETs | Kuo-Cheng Chiang, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang | 2024-08-27 |
| 12068370 | Semiconductor device structure and methods of forming the same | Chi-Yi Chuang, Cheng-Ting Chung, Hou-Yu Chen | 2024-08-20 |
| 12068382 | Dumbbell shaped self-aligned capping layer over source/drain contacts and method thereof | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2024-08-20 |
| 12068372 | Semiconductor device structure integrating air gaps and methods of forming the same | Chih-Ching Wang, Wen-Hsing Hsieh | 2024-08-20 |
| 12068320 | Gate isolation for multigate device | Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Yi-Ruei Jhan, Chih-Hao Wang | 2024-08-20 |
| 12062714 | Back end of line nanowire power switch transistors | Li-Yang Chuang, Ching-Wei Tsai, Wang-Chun Huang | 2024-08-13 |
| 12062693 | Semiconductor device structure and methods of forming the same | Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu +1 more | 2024-08-13 |
| 12057341 | Semiconductor device with gate cut structure and method of forming the same | Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang +2 more | 2024-08-06 |
| 12057507 | Method for manufacturing semiconductor device structure | Kuo-Cheng Ching, Kuan-Ting Pan, Chih-Hao Wang | 2024-08-06 |
| 12057477 | Semiconductor structure with hybrid nanostructures | Wen-Ting Lan, Guan-Lin Chen, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang +1 more | 2024-08-06 |
| 12051693 | Method for manufacturing semiconductor structure with isolation strips | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin | 2024-07-30 |
| 12046516 | Semiconductor device with gate cut feature and method for forming the same | Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Cheng-Chi Chuang +1 more | 2024-07-23 |
| 12046681 | Gate-all-around structure with self substrate isolation and methods of forming the same | Cheng-Ting Chung, Ching-Wei Tsai | 2024-07-23 |
| 12046678 | Vertically-oriented complementary transistor | Chi-Yi Chuang, Hou-Yu Chen | 2024-07-23 |
| 12046644 | Gap spacer for backside contact structure | Li-Zhen Yu, Lin-Yu Huang, Chih-Hao Wang | 2024-07-23 |
| 12046507 | Semiconductor device structure and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang | 2024-07-23 |
| 12040191 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu +1 more | 2024-07-16 |
| 12040329 | Semiconductor device structure and methods of forming the same | Wen-Ting Lan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang | 2024-07-16 |
| 12040371 | Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class | Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang | 2024-07-16 |
| 12040385 | Semiconductor structure and method of manufacturing the same | Chi-Yi Chuang, Ching-Wei Tsai, Chih-Hao Wang | 2024-07-16 |
| 12040386 | Self-aligned epitaxy layer | Kuo-Cheng Chiang, Chih-Hao Wang | 2024-07-16 |
| 12040403 | Semiconductor structure with isolating feature | Yu-Xuan Huang, Ching-Wei Tsai, Hou-Yu Chen | 2024-07-16 |
| 12033899 | Self-aligned metal gate for multigate device | Guan-Lin Chen, Chih-Hao Wang, Ching-Wei Tsai, Shi Ning Ju, Jui-Chien Huang +1 more | 2024-07-09 |