Issued Patents 2024
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12015409 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2024-06-18 |
| 12014982 | Integrated circuit device and method | Cheng-Yu Lin, Jung-Chan Yang, Sheng-Hsiung Chen, Kuo-Nan Yang, Chih-Liang Chen +1 more | 2024-06-18 |
| 12009824 | Clock gating circuit and method of operating the same | Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien +1 more | 2024-06-11 |
| 12009362 | Method of making amphi-FET structure and method of designing | Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Ching-Wei Tsai +1 more | 2024-06-11 |
| 11995390 | Isolation circuit between power domains | Chi-Yu Lu, Ting-Wei Chiang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang +2 more | 2024-05-28 |
| 11990477 | Hybrid fin field-effect transistor cell structures and related methods | Wei-An Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen | 2024-05-21 |
| 11983479 | Integrated circuit, system for and method of forming an integrated circuit | Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang Jui Kao, Lee-Chung Lu, Li-Chun Tien +3 more | 2024-05-14 |
| 11979158 | Integrated circuit device, method and system | Cheng-Yu Lin, Yung-Chen Chien, Jia-Hong GAO, Jerry Chang Jui Kao | 2024-05-07 |
| 11973110 | Semiconductor structure and method of forming the same | Che-Yuan Chang, Chih-Liang Chen | 2024-04-30 |
| 11967596 | Power rail and signal conducting line arrangement | Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Chih-Liang Chen, Li-Chun Tien +1 more | 2024-04-23 |
| 11948886 | Semiconductor device and methods of manufacturing same | Guo-Huei Wu, Chih-Liang Chen, Li-Chun Tien | 2024-04-02 |
| 11942420 | Semiconductor device including recessed interconnect structure | Guo-Huei Wu, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu | 2024-03-26 |
| 11935888 | Integrated circuit having fins crossing cell boundary | Pin-Dai Sue, Ting-Wei Chiang, Ya-Chi Chou, Chi-Yu Lu | 2024-03-19 |
| 11916074 | Double rule integrated circuit layouts for a dual transmission gate | Shih-Wei Peng, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin | 2024-02-27 |
| 11916058 | Multi-bit structure | Shao-Lun Chien, Po-Chun Wang, Chih-Liang Chen, Li-Chun Tien | 2024-02-27 |
| 11907633 | Layout for integrated circuit and the integrated circuit | Cheok-Kei Lei, Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu +3 more | 2024-02-20 |
| 11908851 | Semiconductor device having fin structure | Shun Li Chen, Chung-Te Lin, Pin-Dai Sue, Jung-Chan Yang | 2024-02-20 |
| 11894383 | Staking nanosheet transistors | Pochun Wang, Guo-Huei Wu, Chih-Liang Chen, Li-Chun Tien | 2024-02-06 |
| 11868699 | Inverted integrated circuit and method of forming the same | Pochun Wang, Yu-Jung Chang, Ting-Wei Chiang | 2024-01-09 |
| 11868697 | Base layout cell | Shang-Hsuan CHIU, Chih-Liang Chen, Chi-Yu Lu, Kuang-Ching Chang | 2024-01-09 |
| 11862562 | Integrated circuit conductive line arrangement for circuit structures, and method | Chih-Yu Lai, Chih-Liang Chen, Li-Chun Tien | 2024-01-02 |
| 11862637 | Tie off device | Shao-Lun Chien, Ting-Wei Chiang, Pin-Dai Sue | 2024-01-02 |