Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183629 | Selective hybrid capping layer for metal gates of transistors | Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee +2 more | 2024-12-31 |
| 12176251 | Semiconductor device with profiled work-function metal gate electrode and method of making | Da-Yuan Lee, Hung-Chin Chung, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang +1 more | 2024-12-24 |
| 12170202 | Formation and in-situ etching processes for metal layers | Po-Yu Lin, Chi-Yu Chou, Huai-Tei Yang, Chun-Chieh Wang, Yueh-Ching Pai +3 more | 2024-12-17 |
| 12142530 | Semiconductor device and method of manufacture | Chung-Chiang Wu, Hung-Chin Chung, Chien-Hao Chen, Ching-Hwanq Su | 2024-11-12 |
| 12100751 | Void elimination for gap-filling in high-aspect ratio trenches | Chih-Hsiang Fan, Tsung-Han Shen, Jia-Ming Lin, Wei-Chin Lee, Chi On Chui | 2024-09-24 |
| 12087767 | Method of tuning threshold voltages of transistors | Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Chi On Chui +2 more | 2024-09-10 |
| 12040235 | Semiconductor device and method of manufacture | Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu +7 more | 2024-07-16 |
| 11961768 | CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same | Ya-Wen Chiu, Da-Yuan Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan +1 more | 2024-04-16 |
| 11916146 | Gate resistance reduction through low-resistivity conductive layer | Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Chien-Hao Chen | 2024-02-27 |
| 11875591 | Light guiding member and fingerprint identification module having the same | Tsung-Yi Lu | 2024-01-16 |