Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12170280 | Method of manufacturing gate structure and method of manufacturing fin-field effect transistor | Ji-Cheng Chen, Kuan-Ting Liu, Shih-Hang Chiu | 2024-12-17 |
| 12142531 | Pre-deposition treatment for FET technology and devices formed thereby | Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee +3 more | 2024-11-12 |
| 12142530 | Semiconductor device and method of manufacture | Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen | 2024-11-12 |
| 12113120 | Gate electrode having a work-function layer including materials with different average grain sizes | Ru-Shang Hsiao, Pin Chia Su, Ying Hsin Lu, Ling-Sung Wang | 2024-10-08 |
| 12033893 | Contact plug with impurity variation | Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung | 2024-07-09 |
| 12021147 | FinFET structures and methods of forming the same | Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu | 2024-06-25 |
| 12021130 | Circuit structure with gate configuration | Ru-Shang Hsiao, Ying Hsin Lu, Pin Chia Su, Ling-Sung Wang | 2024-06-25 |
| 11961891 | Structure for metal gate electrode and method of fabrication | Ru-Shang Hsiao, Pohan Kung, Ying Hsin Lu, I-Shan Huang | 2024-04-16 |
| 11949000 | Metal gate structures and methods of fabricating the same in field-effect transistors | Ru-Shang Hsiao, Pin Chia Su, Ying Hsin Lu, I-Shan Huang | 2024-04-02 |
| 11935957 | Geometry for threshold voltage tuning on semiconductor device | Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau +3 more | 2024-03-19 |