Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176251 | Semiconductor device with profiled work-function metal gate electrode and method of making | Da-Yuan Lee, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang +1 more | 2024-12-24 |
| 12142530 | Semiconductor device and method of manufacture | Chung-Chiang Wu, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su | 2024-11-12 |
| 12142531 | Pre-deposition treatment for FET technology and devices formed thereby | Cheng-Yen Tsai, Chung-Chiang Wu, Tai-Wei Hwang, Wei-Chin Lee, Da-Yuan Lee +3 more | 2024-11-12 |
| 12087637 | Semiconductor device and method of manufacture | Chung-Chiang Wu, Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Cheng-Lung Hung +1 more | 2024-09-10 |
| 12087767 | Method of tuning threshold voltages of transistors | Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hsien-Ming Lee, Chi On Chui +2 more | 2024-09-10 |
| 12051753 | Fin field-effect transistor device having hybrid work function layer stack | Chun-Neng Lin, Ming-Hsi Yeh, Hsin-Yun Hsu | 2024-07-30 |
| 12040235 | Semiconductor device and method of manufacture | Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu +7 more | 2024-07-16 |
| 12021145 | Fin field-effect transistor device having hybrid work function layer stack | Chun-Neng Lin, Ming-Hsi Yeh, Hsin-Yun Hsu | 2024-06-25 |
| 11916146 | Gate resistance reduction through low-resistivity conductive layer | Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hsien-Ming Lee, Chien-Hao Chen | 2024-02-27 |