| 12171103 |
Multi-input threshold gate having stacked and folded non-planar capacitors |
Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni |
2024-12-17 |
| 12166011 |
Method of forming an artificial intelligence processor with three-dimensional stacked memory |
Rajeev Kumar Dokania, Sasikanth Manipatruni, Debo Olaosebikan |
2024-12-10 |
| 12155383 |
Reset mechanism for an adder or a multiplier having paraelectric material |
Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2024-11-26 |
| 12147747 |
Area oriented logic synthesis |
Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania |
2024-11-19 |
| 12147941 |
Iterative monetization of precursor in process development of non-linear polar material and devices |
Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Somilkumar J. Rathi +3 more |
2024-11-19 |
| 12142310 |
Method of fabricating pedestal based memory devices using pocket integration |
Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2024-11-12 |
| 12137574 |
Integration of ferroelectric memory devices having stacked electrodes with transistors |
Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Gaurav Thareja |
2024-11-05 |
| 12126339 |
Apparatus with selectable majority gate and combinational logic gate outputs |
Sasikanth Manipatruni, Rafael Rios, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania +1 more |
2024-10-22 |
| 12118327 |
Ripple carry adder with inverted ferroelectric or paraelectric based adders |
Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni |
2024-10-15 |
| 12118330 |
Low power multiplier with non-linear polar material based reset mechanism with sequential reset |
Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2024-10-15 |
| 12113097 |
Ferroelectric capacitor integrated with logic |
Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh |
2024-10-08 |
| 12108607 |
Devices with continuous electrode plate and methods of fabrication |
Noriyuki Sato, Debraj Guhabiswas, Tanay Gosavi, Niloy Mukherjee, Sasikanth Manipatruni |
2024-10-01 |
| 12108608 |
Memory devices with dual encapsulation layers and methods of fabrication |
Noriyuki Sato, Debraj Guhabiswas, Tanay Gosavi, Niloy Mukherjee, Sasikanth Manipatruni |
2024-10-01 |
| 12107579 |
Method for conditioning majority or minority gate |
Rajeev Kumar Dokania, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh +1 more |
2024-10-01 |
| 12108609 |
Memory bit-cell with stacked and folded planar capacitors |
Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni |
2024-10-01 |
| 12094511 |
Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor bit-cell |
Rajeev Kumar Dokania, Mustansir Yunus Mukadam, Tanay Gosavi, James David Clarkson, Neal Reynolds +1 more |
2024-09-17 |
| 12094923 |
Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices |
Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more |
2024-09-17 |
| 12096638 |
One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset |
Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni |
2024-09-17 |
| 12088297 |
Majority gate based low power ferroelectric based adder with reset mechanism |
Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more |
2024-09-10 |
| 12086410 |
Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer |
Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni |
2024-09-10 |
| 12087730 |
Multi-input threshold gate having stacked and folded planar capacitors with and without offset |
Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni |
2024-09-10 |
| 12079475 |
Ferroelectric memory chiplet in a multi-dimensional packaging |
Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni |
2024-09-03 |
| 12069866 |
Pocket integration process for embedded memory |
Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni |
2024-08-20 |
| 12062584 |
Iterative method of multilayer stack development for device applications |
Sasikanth Manipatruni, Niloy Mukherjee, Noriyuki Sato, Tanay Gosavi, Mauricio Manfrini +4 more |
2024-08-13 |
| 12041785 |
1TnC memory bit-cell having stacked and folded non-planar capacitors |
Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni |
2024-07-16 |