Issued Patents 2024
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12147747 | Area oriented logic synthesis | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-11-19 |
| 11967954 | Majority or minority logic gate with non-linear input capacitors without reset | Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-04-23 |
| 11922105 | Computer-aided design tool for minimum gate count initialization | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-03-05 |
| 11861278 | Computer-aided design tool for gate pruning | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-02 |
| 11861279 | Computer-aided design tool for inverter minimization | Ikenna Odinaka, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-01-02 |