Issued Patents 2024
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11899613 | Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging | Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni | 2024-02-13 |
| 11903219 | Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors | Rajeev Kumar Dokania, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni | 2024-02-13 |
| 11901891 | Asynchronous consensus circuit with stacked ferroelectric planar capacitors | Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-02-13 |
| 11894417 | Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2024-02-06 |
| 11888479 | Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism | Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-30 |
| 11875836 | Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing | Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania | 2024-01-16 |
| 11869843 | Integrated trench and via electrode for memory device applications and methods of fabrication | Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more | 2024-01-09 |
| 11871584 | Multi-level hydrogen barrier layers for memory applications | Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more | 2024-01-09 |
| 11871583 | Ferroelectric memory devices | Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-09 |
| 11869928 | Dual hydrogen barrier layer for memory devices | Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more | 2024-01-09 |
| 11869562 | Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion | Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania | 2024-01-09 |
| 11861279 | Computer-aided design tool for inverter minimization | Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania | 2024-01-02 |
| 11863184 | Asynchronous validity tree circuit using multi-function threshold gate with input based adaptive threshold | Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2024-01-02 |
| 11863183 | Low power non-linear polar material based threshold logic gate multiplier | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2024-01-02 |
| 11862517 | Integrated trench and via electrode for memory device applications | Noriyuki Sato, Niloy Mukherjee, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania +2 more | 2024-01-02 |
| 11861278 | Computer-aided design tool for gate pruning | Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania | 2024-01-02 |