Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12137574 | Integration of ferroelectric memory devices having stacked electrodes with transistors | Sasikanth Manipatruni, Rajeev Kumar Dokania, Gaurav Thareja, Amrita Mathuriya | 2024-11-05 |
| 12126339 | Apparatus with selectable majority gate and combinational logic gate outputs | Sasikanth Manipatruni, Rafael Rios, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania +1 more | 2024-10-22 |
| 12113097 | Ferroelectric capacitor integrated with logic | Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya | 2024-10-08 |
| 12107579 | Method for conditioning majority or minority gate | Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes +1 more | 2024-10-01 |
| 12094923 | Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2024-09-17 |
| 12088297 | Majority gate based low power ferroelectric based adder with reset mechanism | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2024-09-10 |
| 11908704 | Method of fabricating a perovskite-material based planar capacitor using rapid thermal annealing (RTA) methodologies | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2024-02-20 |
| 11894417 | Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies | Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren +8 more | 2024-02-06 |
| 11863183 | Low power non-linear polar material based threshold logic gate multiplier | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2024-01-02 |