Issued Patents 2024
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12137169 | Low latency post-quantum signature verification for fast secure-boot | Santosh Ghosh, Sanu K. Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar +1 more | 2024-11-05 |
| 12047485 | Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations | Raghavan Kumar, Xiaosen Liu, Harish Krishnamurthy, Sanu K. Mathew | 2024-07-23 |
| 11917053 | Combined SHA2 and SHA3 based XMSS hardware accelerator | Santosh Ghosh, Sanu K. Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar +1 more | 2024-02-27 |