Issued Patents 2023
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854649 | Temperature-compensated time estimate for a block to reach a uniform charge loss state | Patrick R. Khayat, Steven Michael Kientz, Sivagnanam Parthasarathy, Vamsi Pavan Rayaprolu | 2023-12-26 |
| 11847317 | Managing bin placement for block families of a memory device based on trigger metric valves | Shane Nowell | 2023-12-19 |
| 11837307 | Managing error-handling flows in memory devices | Kishore Kumar Muchherla, Shane Nowell, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2023-12-05 |
| 11837291 | Voltage offset bin selection by die group for memory devices | Vamsi Pavan Rayaprolu, Michael Sheperek, Larry J. Koudele, Shane Nowell | 2023-12-05 |
| 11829245 | Multi-layer code rate architecture for copyback between partitions with different code rates | Kishore Kumar Muchherla, Sivagnanam Parthasarathy, James Fitzpatrick, Mark A. Helm | 2023-11-28 |
| 11823748 | Voltage bin calibration based on a temporary voltage shift offset | Kishore Kumar Muchherla, Karl D. Schuh, Xiangang Luo, Shane Nowell, Devin M. Batutis +4 more | 2023-11-21 |
| 11823722 | Determining voltage offsets for memory read operations | Kishore Kumar Muchherla, Sampath K. Ratnam, Shane Nowell, Peter Feeley, Sivagnanam Parthasarathy | 2023-11-21 |
| 11797205 | Measurement of representative charge loss in a block to determine charge loss state | Patrick R. Khayat, Steven Michael Kientz, Sivagnanam Parthasarathy, Vamsi Pavan Rayaprolu | 2023-10-24 |
| 11783901 | Multi-tier threshold voltage offset bin calibration | Kishore Kumar Muchherla, Shane Nowell, Karl D. Schuh, Jiangang Wu, Devin M. Batutis +1 more | 2023-10-10 |
| 11777522 | Bit flipping decoder with dynamic bit flipping criteria | Sivagnanam Parthasarathy, Eyal En Gad | 2023-10-03 |
| 11755478 | Block family combination and voltage bin selection | Michael Sheperek, Larry J. Koudele, Shane Nowell | 2023-09-12 |
| 11748013 | Grouping blocks based on power cycle and power on time | Kishore Kumar Muchherla, Jiangang Wu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Peter Feeley +1 more | 2023-09-05 |
| 11735254 | Error avoidance based on voltage distribution parameters of blocks | Shane Nowell, Steven Michael Kientz, Michael Sheperek, Kishore Kumar Muchherla, Larry J. Koudele +1 more | 2023-08-22 |
| 11727994 | Performing threshold voltage offset bin selection by package for memory devices | Michael Sheperek, Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Larry J. Koudele | 2023-08-15 |
| 11720286 | Extended cross-temperature handling in a memory sub-system | Vamsi Pavan Rayaprolu, Sampath K. Ratnam, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell +2 more | 2023-08-08 |
| 11722151 | Bit flipping decoder based on soft information | Sivagnanam Parthasarathy | 2023-08-08 |
| 11714710 | Providing data of a memory system based on an adjustable error rate | Larry J. Koudele, Michael Sheperek, Patrick R. Khayat, Sampath K. Ratnam | 2023-08-01 |
| 11711095 | Bit flipping low-density parity-check decoders with low error floor | Sivagnanam Parthasarathy | 2023-07-25 |
| 11709727 | Managing error-handling flows in memory devices | Kishore Kumar Muchherla, Shane Nowell, Sampath K. Ratnam, Peter Feeley, Sivagnanam Parthasarathy +2 more | 2023-07-25 |
| 11709734 | Error correction with syndrome computation in a memory device | Patrick R. Khayat, Sivagnanam Parthasarathy | 2023-07-25 |
| 11710527 | Mitigating a voltage condition of a memory cell in a memory sub-system | Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy +2 more | 2023-07-25 |
| 11705925 | Dynamic bit flipping order for iterative error correction | Sivagnanam Parthasarathy | 2023-07-18 |
| 11705193 | Error avoidance based on voltage distribution parameters | Shane Nowell, Steven Michael Kientz, Michael Sheperek, Kishore Kumar Muchherla, Larry J. Koudele +1 more | 2023-07-18 |
| 11705192 | Managing read level voltage offsets for low threshold voltage offset bin placements | Kishore Kumar Muchherla, Michael Sheperek, Shane Nowell | 2023-07-18 |
| 11704217 | Charge loss scan operation management in memory devices | Michael Sheperek, Steven Michael Kientz, Shane Nowell, Kishore Kumar Muchherla, Larry J. Koudele | 2023-07-18 |